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PROCEEDINGS VOLUME 4692

Design, Process Integration, and Characterization for Microelectronics
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Volume Details

Volume Number: 4692
Date Published: 12 July 2002
Softcover: 58 papers (644) pages
ISBN: 9780819444394

Table of Contents
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Effect of metrology time delay on overlay APC
Author(s): Alan Carlson; Debra DiBiase
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Profile parameter accuracy determined from scatterometric measurements
Author(s): Rayan M. Al-Assaad; Emmanuel M. Drege; Dale M. Byrne
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2001 metrology roadmap: process control through amplification and averaging microscopic changes
Author(s): Alain C. Diebold
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Prediction of light scattering from particles on a filmed surface using discrete-dipole approximation
Author(s): Haiping Zhang; E. Dan Hirleman
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Industry survey of automatic defect classification technologies, methods, and performance
Author(s): Kenneth W. Tobin; Fred Lakhani; Thomas P. Karnowski
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Submicron particle identification by compositional defect review using Auger analysis
Author(s): Kenton D. Childs; Dennis F. Paul; Tomohiko Morohashi; Stephen P. Clough
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Detection of semiconductor defects using a novel fractal encoding algorithm
Author(s): Shaun S. Gleason; Regina K. Ferrell; Thomas P. Karnowski; Kenneth W. Tobin
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Automated residual metal inspection
Author(s): Rajesh Tiwari; Joel Strupp; Prasad S. Terala; Doron Shoham
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Defect detection for short-loop process and SRAM-cell optimization by using addressable failure site-test structures (AFS-TS)
Author(s): Kelvin Yih-Yuh Doong; Sunnys Hsieh; S. C. Lin; J. R. Wang; Binson Shen; L. J. Hung; J. C. Guo; I. C. Chen; K. L. Young; Charles Ching-Hsiang Hsu
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Evolving paradigm for fab revenue optimization
Author(s): Ramakrishna Akella; Kristin Fridgeirsdottir; Andrew Skumanich
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Methodology for defect impact studies under conditions of low sampling statistics
Author(s): Andrew Skumanich; Elmira Ryabova
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Isolating causes of yield excursions with decision tress and commonality
Author(s): Peter Waksman
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Using an image retrieval system for image data management
Author(s): Thomas P. Karnowski; Kenneth W. Tobin; Regina K. Ferrell; William Bruce Jatko; Fred Lakhani
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Wafer-level fault detection and classification on a photo track in a high volume fab
Author(s): Timothy L. Jackson; Richard J. Markle; Clinton W. Miller; Edward C. Stewart; Robert A. Crowell
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Meeting the challenges of process module and fab-wide active control for 300 mm, 130 nm, and beyond
Author(s): Israel Beinglass
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Just-in-time adaptive disturbance estimation for run-to-run control of photolithography overlay
Author(s): Stacy K. Firth; W. Jarrett Campbell; Thomas F. Edgar
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Common APC architecture for 200- and 300-mm etch
Author(s): Merritt Funk; Kevin Lally; Radha Sundararajan
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Microloading characterization of 300-mm etch and CMP tools
Author(s): Karl E. Mautz
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GOI characterization of 300-mm furnace tools
Author(s): Karl E. Mautz
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Thermo- and galvanomagnetic investigations of semiconductors at high pressure up to 30 GPa
Author(s): Sergey V. Ovsyannikov; Vladimir V. Shchennikov
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SEM review and discrete inspection of optically invisible defects in a production environment
Author(s): Benoit Hinschberger; Christine Gombar; Laurent Ithier; Laurent Couturier; Boris Sherman; Ofer Rothlevi; Ariel Ben-Porath
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Defect topographic maps using a non-Lambertian photometric stereo method
Author(s): Sergio David Serulnik
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Direct to digital holography for semiconductor wafer defect detection and review
Author(s): C. E. Thomas; Tracy M. Bahm; Larry R. Baylor; Philip R. Bingham; Steven W. Burns; Matt Chidley; Long Dai; Robert J. Delahanty; Christopher J. Doti; Ayman El-Khashab; Robert L. Fisher; Judd M. Gilbert; James S. Goddard; Gregory R. Hanson; Joel D. Hickson; Martin A. Hunt; Kathy W. Hylton; George C. John; Michael L. Jones; Ken R. Macdonald; Michael W. Mayo; Ian McMackin; Dave R. Patek; John H. Price; David A. Rasmussen; Louis J. Schaefer; Thomas R. Scheidt; Mark A. Schulze; Philip D. Schumaker; Bichuan Shen; Randall G. Smith; Allen N. Su; Kenneth W. Tobin; William R. Usry; Edgar Voelkl; Karsten S. Weber; Paul G. Jones; Robert W. Owen
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Nondestructive testing of damage layers in semiconductor materials by surface acoustic waves
Author(s): Dieter Schneider; Eva Stiehl; Ralf Hammer; Andreas Franke; Richard P. Riegert; Thomas Schuelke
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Crossing the divide between lithography and chip design
Author(s): William H. Arnold; J. Fung Chen; Kurt E. Wampler
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Approaching the one billion transistor logic product: process and design challenges
Author(s): George E. Sery
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Enabling the 70-nm technology node with 193-nm altPSM lithography
Author(s): Lars W. Liebmann; Jennifer Lund; Ioana C. Graur; Fook-Luen Heng; Carlos A. Fonseca; James Culp; Allen H. Gabor
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Developing an integrated imaging system for the 70-nm node using high numerical aperture ArF lithography
Author(s): John S. Petersen; James V. Beach; David J. Gerold; Mark John Maslow
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Exposing the DUV SCAAM: 75-nm imaging on the cheap
Author(s): David Levenson; Takeaki Ebihara
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GDS-3 initiative: advanced design-through-chip infrastructure for subwavelength technology
Author(s): Robert C. Pack; Mitchell D. Heins; Ahmad R. Chatila; Victor V. Boksha; D. Cottrell; C. Neil Berglund; J. Hogan; F. James; T. Vucurevich; M. Bales; K. Shimasaki
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Model-based WYSIWYG: dimensional metrology infrastructure for design and integration
Author(s): Alexander Starikov
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Chip-level line-width prediction methodology
Author(s): Pat LaCour; Emile Y. Sahouria; Yuri Granik
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Verifying RET mask layouts
Author(s): Jeffrey P. Mayhew; Michael L. Rieger; Jiangwei Li; Lin Zhang; Zongwu Tang; James P. Shiely
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IC yield prediction and analysis using semi-empirical yield models and test data
Author(s): Dennis J. Ciplickas; Mariusz Niewczas; Roland Ruehl; Brian Stine; Rakesh R. Vallishayee; Wojtek Wojciak
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New method for reducing across-chip poly-CD variation with statistical OPC/gauge capability analysis
Author(s): Hidetoshi Ohnuma; Koji Kikuchi; Hiroichi Kawahira
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Impact of subwavelength CD tolerance on device performance
Author(s): Artur P. Balasinski; Linard Karklin; Valery Axelrad
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Design-process integration and shared red bricks
Author(s): Andrew B. Kahng
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Relevance of TCAD to process-aware design
Author(s): Vivek K. Singh; Jorge Garcia-Colevatti
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Improving device performance and process manufacturability through the use of TCAD
Author(s): Kaiping Liu; Jeff Z. Wu; Jihong Chen; Amitabh Jain; Manoj Mehrotra
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Monte-Carlo methods for chemical-mechanical planarization on multiple-layer and dual-material models
Author(s): Yu Chen; Andrew B. Kahng; Gabriel Robins; Alexander Zelikovsky
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Infrastructure for model-based OPC development in the deep submicron era
Author(s): Zhengrong Zhu; Dennis J. Ciplickas; Andrzej J. Strojwas
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Validation of the aberration-pattern-matching OPC strategy
Author(s): Frank E. Gennari; Garth Robins; Andrew R. Neureuther
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Characterizing the process window of a double-exposure dark-field alternating phase-shift mask
Author(s): Chris A. Mack
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Symmetry enhancement method for process modeling and its applications in IC design and OPC
Author(s): Junjiang Lei; Michael Sanie; David K.H. Lay
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Role of mask acuity in advanced lithographic process design
Author(s): Peter D. Buck
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Evolution and integration of optimal IC design: performance and manufacturing issues
Author(s): Daniel C. Cole; So-Yeon Baek; Xima Zhang
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Highly manufacturable capacitor-less 1T-DRAM concept
Author(s): Pierre C. Fazan; Serguei Okhonin; Mikhail Nagoga; Jean-Michel Sallese
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Investigation of the physical and practical limits of dense-only phase-shift lithography for circuit feature definition
Author(s): Brian Tyrrell; Michael Fritze; Renee D. Mallen; Bruce Wheeler; Peter D. Rhyins; Patrick M. Martin
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Exact computation of scalar 2D aerial imagery
Author(s): Ronald L. Gordon
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RET-compliant cell generation for sub-130-nm processes
Author(s): Juan Andres Torres; David Chow; Paul de Dood; Daniel J. Albers
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Model-based OPC for sub-resolution assist feature enhanced layouts
Author(s): Pat LaCour; Edwin A. Pell; Yuri Granik; Thuy Do
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Implications of tiling for performance and design flow
Author(s): Ertugrul Demircan; Ruiqi Tian; Warren D. Grobman
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Adoption costs and hierarchy efficiency for 100 nm and beyond
Author(s): Franklin M. Schellenberg
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Development of a sub-100nm integrated imaging system using chromeless phase-shifting imaging with very high NA KrF exposure and off-axis illumination
Author(s): John S. Petersen; Will Conley; Bernard J. Roman; Lloyd C. Litt; Kevin Lucas; Wei Wu; Douglas J. Van Den Broeke; J. Fung Chen; Thomas L. Laidig; Kurt E. Wampler; David J. Gerold; Mark John Maslow; Robert John Socha; Judith van Praagh; Richard Droste
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248-nm photolithography compatibility on low-k dielectrics in BEOL interconnects
Author(s): Hyesook Hong; Guoqiang Xing; Andrew Mckerrow; Tae S. Kim; Patricia B. Smith
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Error budget for a 193-nm complementary phase-shift mask
Author(s): Nicholas K. Eib; Olga Kobozeva; Chris Neville; Ebo H. Croffie
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Design verification flow for model-assisted double-dipole decomposition
Author(s): Juan Andres Torres; Franklin M. Schellenberg; Olivier Toublan
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Robust methodology for state-of-the-art embedded SRAM bitcell design
Author(s): Mark J. Craig; John S. Petersen; Joshua Lund; David J. Gerold; Nien-Po Chen
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Panel discussion summary: do we need a revolution in design and process integration to enable sub-100-nm technology nodes?
Author(s): Warren D. Grobman
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