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Proceedings of SPIE Volume 4525

Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III
Editor(s): John Schewel; Peter M. Athanas; Philip B. James-Roxby; John T. McHenry
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Softcover $105.00 * $105.00 *

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Volume Details

Volume Number: 4525
Date Published: 24 July 2001
Softcover: 18 papers (180) pages
ISBN: 9780819442499

Table of Contents
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Fault injection emulator for field-programmable gate arrays
Author(s): Thomas Slaughter; Charles Stroud; John Emmert; Brandon Skaggs
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Transformation from C-program to circuitry for a dynamically reconfigurable cell array processor
Author(s): Takayuki Morishita; Kiyotaka Komoku; Fumihiro Hatano; Iwao Teramoto
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Designing application-specific cores using JBits: a run-time parameterizable FIR filter
Author(s): Philip B. James-Roxby
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Temporal partitioning of circuits for advanced partially reconfigurable systems
Author(s): Rajanikant Mohan; Aravind R. Dasu; Sethuraman Panchanathan
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Model-based performance analysis for reconfigurable coprocessors
Author(s): Stephen M. Charlwood; Jon P. Mangnall; Steven F. Quigley
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Configuration subsystem design exploration for domain-specific reconfigurable technologies
Author(s): Milan Vasilko
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Programming high-performance reconfigurable computers
Author(s): Melissa C. Smith; Gregory D. Peterson
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Real-time debugger with bitstream configurator and C language design control for FPGAs
Author(s): Steve Casselman; John Schewel; Frank Wartel
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Digital FPGA implementation for Bellman-Ford computation
Author(s): Wai-ming Fung; Hoi-shing Ng; Kai-pui Lam
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Reconfiguring an FPGA-based RISC for LNS arithmetic
Author(s): Mark G. Arnold; Mark D. Winkel
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Highly reconfigurable communication protocol multiplexing element for SCOPH
Author(s): Gordon Brebner
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Spatially reconfigurable module for FIR filters
Author(s): Toomas P. Plaks
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Run-time reconfigurable 2D discrete wavelet transform using JBits
Author(s): Jonathan Ballagh; Peter M. Athanas; Eric R. Keller
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Network processor architecture for flexible buffer management in very high speed line interfaces
Author(s): Shimonishi Hideyuki; Murase Tutomu
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Reconfigurable processors for handhelds and wearables: application analysis
Author(s): Rolf Enzler; Marco Platzner; Christian Plessl; Lothar Thiele; Gerhard Troester
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Variable length decoder on dynamically reconfigurable cell array processor
Author(s): Kiyotaka Komoku; Takayuki Morishita; Fumihiro Hatano; Iwao Teramoto
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XHWIF: a portable hardware interface for reconfigurable computing
Author(s): Prasanna Sundararajan; Steven A. Guccione; Delon Levi
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Signal processing for multiuser wireless systems on reconfigurable platforms
Author(s): Joseph Thomas
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