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Challenges in Process Integration and Device Technology
Editor(s): David Burnett; Shin'ichiro Kimura; Bhanwar Singh
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Volume Details

Volume Number: 4181
Date Published: 18 August 2000
Softcover: 40 papers (354) pages
ISBN: 9780819438423

Table of Contents
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Evolution of semiconductor process technology
Author(s): Trung Tri Doan
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Subwavelength optical lithography
Author(s): Tsuneo Terasawa
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Feasibility of very low k1(=0.31) KrF lithography
Author(s): Insung Kim; Byeongsoo Kim; Junghyun Lee; Hanku Cho; Joo-Tae Moon
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Pattern placement errors: application of in-situ interferometer-determined Zernike coefficients in determining printed image deviations
Author(s): William R. Roberts; Christopher J. Gould; Adlai H. Smith; Ken Rebitz
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MEEF measurement and model verification for 0.3-k1 lithography
Author(s): Colin R. Parker; Michael T. Reilly
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Benchmarking of advanced CD-SEMs against a new unified specification for sub-0.18-um lithography
Author(s): Alain G. Deleporte; John A. Allgair; Charles N. Archie; G. William Banke; Michael T. Postek; Jerry E. Schlesinger; Andras E. Vladar; Arnold W. Yanof
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Effects of advanced illumination schemes on design manufacturability and interactions with optical proximity corrections
Author(s): Luigi Capodieci; Juan Andres Torres; Robert John Socha; Uwe Hollerbach; J. Fung Chen; Christian van Os; Yuri Granik; Olivier Toublan; Nicolas B. Cobb
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Deciphering and encoding product overlay: hidden errors
Author(s): Christopher J. Gould; William R. Roberts; Francis G. Goodwin
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Automated OPC optimization using in-line CD-SEM
Author(s): Bo Su; Mina Menaker; Nadav Haas; Ramkumar Subramanian; Bhanwar Singh
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Advanced lithography kits: serifs and hammerhead
Author(s): Hang-Yip Liu; Steffen F. Schulze; Alan C. Thomas; Anne E. McGuire; Michael Cross
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Investigations on the impacts of misalignment in the integration of 0.18-u multilevel interconnect
Author(s): Teck Jung Tang; Juan Boon Tan; Sajan R. Marokkey; Tae Jong Lee; Alan Cuthbertson
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Novel electrical alignment structure
Author(s): Todd Lukanc
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Thickness-dependent optical and dielectric behaviors of low-k polymer thin films
Author(s): Hyungkun Kim; Frank G. Shi; Bin Zhao; Maureen R. Brongo
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Design and process issues affecting performance of optical interconnects on ICs
Author(s): Bharat L. Bhuva; Dong Jiang; David V. Kerns; Sherra E. Kerns
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Optical coherent control in materials with stripe phase
Author(s): Sher Alam; Mohammed Obaidur Rahman
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High-performance vs. low-power technology roadmaps: how are they different?
Author(s): Dirk Wristers
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Planarization approaches to via-first dual-damascene processing
Author(s): Edward K. Pavelchek; Marjorie Cernigliaro; Peter Trefonas; Manuel doCanto
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Etching characteristics of organic low-k dielectrics in the helicon-wave plasma etcher for 0.15-um damascene architecture
Author(s): Jia-Min Shieh; T. C. Wei; C. H. Liu; Shich-Chang Suen; Bau-Tong Dai
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Modeling of the removal rate in chemical mechanical polishing
Author(s): Van H. Nguyen; Frank G. Shi
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Process development of 50-A IMP Ti with <2% thickness uniformity for 300-mm iLB
Author(s): Xinyu Zhang; Ian Pancham; Anthony C.-T. Chan; Mani Subamani; John Forster; Jim von Gogh
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Isothermal test as a WLR monitor for Cu interconnects
Author(s): Amit P. Marathe; Van Pham; Jay Chan; Jorg-Oliver Weidner; Volker Heinig; Steffi Thierbach
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Effect of stress and dopant redistribution on trench-isolated narrow devices
Author(s): Gregory S. Scott; Faran Nouri; Mark E. Rubin; Martin Manley; Peter Stolk
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Yield-limiting NMOSFET gate depletion in a deep submicrometer CMOS process
Author(s): Martin P. Karnett; Steven G. Qian; Todd Mitchell; Vijaya Subramaniam; Harlan Sur; Bradley J. Haby; Hunter B. Brugge
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Backwafer optical lithography and wafer distortion in substrate transfer technologies
Author(s): Henk W. Van Zeijl; J. Slabbekoorn; L. K. Nanver; Paul W.L. Van Dijk; Axel Berthold; T. Machielsen
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Scaling considerations for MOSFET devices with 25-nm channel lengths
Author(s): Samar K. Saha
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Correlation between the reliability of ultrathin ISSG SiO2 and hydrogen content
Author(s): Tien-Ying Luo; Husam N. Al-Shareef; George A. Brown; Michael A. Laughery; Victor H. C. Watt; Arun Karamcheti; Mike D. Jackson; Howard R. Huff
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Evaluation of Schottky contact parameters in MSM-photodiode structures
Author(s): Stanislav V. Averine; Yuen Chuen Chan; Yee Loy Lam
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Measuring thicknesses of native oxide, crystalline-silicon, and buried oxide layers and the interface roughnesses of SOI
Author(s): Iris Bloomer; George G. Li; A. Rahim Forouhi; A. Auberton-Herve; Andrew Wittkower
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Microstructuring with 193-nm laser radiation
Author(s): Lin Zhang; Qihong Lou; Yunrong Wei; Feng Huang
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Is lithography ready for 300 mm?
Author(s): Alain B. Charles; Clint Haris; Steffen R. Hornig; Dietmar Ganz; Thorsten Schedel; Guenther Hraschan; Wolfram Koestler; John G. Maltabes; Karl E. Mautz; Sebastian Schmidt; Ralf Schuster
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Efficient resist edgebead removal for thick I-line resist coating application on TEL Mark 7 track sytem
Author(s): Quang Tran
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Prospective technology for system-on-a-chip: N2 implant followed by VHP O2 reoxidation
Author(s): Tien-Ying Luo; Husam N. Al-Shareef; George A. Brown; Victor H. C. Watt; Arun Karamcheti; Mike D. Jackson; Howard R. Huff; Bob Evans; Chongmok Lee; Hong-Fa Luan; Dim-Lee Kwong
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Low-k etch/ash for copper dual damascene
Author(s): Tomoki Suemasa; Masaru Nishino; Kouichiro Inazawa; Vaidyanathan Balasubramanian; Eiichi Nishimura
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Increasing degree of homogeneity of electrical parameters of neutron-transmuted silicon
Author(s): Shermakhmat Makhkamov; Nigmatilla A. Tursunov; Maripjon Ashurov; Zokirkhon M. Khakimov
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Field effects in the dielectrics coated by ITO films
Author(s): Jadwiga Olesik; Zygmunt Olesik
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Influence of the varyband layer of the amorphous hydrogenated silicon-germanium on the current-volt characteristics of the n+(a-Si:H)-i(a-Si1-xGex:H)-n+(a-Si:H)-structures
Author(s): Rustam R. Kabulov
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Laser-induced structure defects and their use for modification of properties of (Cd,Hg)Te epitaxial layers end CdTe cyrstals
Author(s): Apollinariy Zaginey; Bohdan K. Kotlyarchuk; Yuriy Syvenkyy
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Design and fabrication of a GXGA microdisplay chip
Author(s): Paul M. F. Colson; Freddy De Pestel; Marnix Tack; Gust Schols; Herbert De Smet; Jean Van den Steen; Andre Van Calster
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Low-energy neutral processing and process characterization
Author(s): Xianmin Tang; Dennis M. Manos; Qi Wang; Chris A. Nichols
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Technology of electroplating copper with low-K material a-C:F for 0.15-um damascence interconnection
Author(s): Jia-Min Shieh; Shich-Chang Suen; Kuen-Chaung Lin; Shih-Chieh Chang; Bau-Tong Dai; Chia-Fu Chen; Ming Shiann Feng
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