For the past years the number of transistors integrated into a single chip has doubled every one to two years; that trend has not slowed down. Actually, it has accelerated every time we hit a technology barrier point. New developments in process and equipment technology have enabled us to follow Moore's law to reduce the average dimension of the physical features of integrated circuits from 10micrometers down to .1micrometers . What will be the limit be. 0.01micrometers and 120 inches. We will not reach it within this decade.

Production of fine features is vital for increasing integration degree of ultra-large scale integrated (ULSI) devices. Although optical lithography has been widely used for mass-production of ULSIs, the conventional method which utilize large numerical aperture lens and short wavelength exposure is limited by lens manufacturing and narrow depth of focus. To overcome this limit, several resolution enhancement techniques (RETs) have been required and proposed. The RETs include various types of phase shift mask, off-axis illumination, the pupil filtering techniques, and associated techniques. Optical proximity effect correction technique has also been developed to apply these RETs effectively, especially in the sub-wavelength optical lithography. This paper introduces typical RETs with potential and discusses the imaging characteristics of those techniques comparing with conventional binary mask technique.

We observed the feasibility of very low k1(equals0.31) lithography for DRAM device using currently available high NA KrF scanner. Well-known resolution enhancement techniques (RET) such as off- axis illumination (OAI) and attenuated phase shifting mask were used in combination to define critical DRAM cell patterns of 0.11micrometers half pitch design rule device with 0.7NA KrF scanner. Strong OAI illumination source was applied to further enhance the image contrast up to the required level for patterning. Very large iso-dense bias and narrow depth of focus (DOF) of isolated features which define usable DOF(UDOF) are emerging critical issues to be solved except the very fundamental lens aberrations. Combined problems of large I-D bias and narrow UDOF could be solved by applying selective bias and assistant line patterns to isolated line. Optical proximity correction rules; selective bias and assist pattern, were generated from simulated and empirical experiments. This technology might be considered as one of the alternatives that need to fill the time and design rule gap between 0.13micrometers with KrF and sub-0.10micrometers with ArF. KrF lithography technology of 0.31k1 can be extended to ArF generation and contribute to the extension of 'optics forever' scenario.

Several ideas have recently been presented which attempt to measure and predict lens aberrations for new low k1 imaging systems. Abbreviated sets of Zernike coefficients have been produced and used to predict Across Chip Linewidth Variation. Empirical use of the wavefront aberrations can now be used in commercially available lithography simulators to predict pattern distortion and placement errors. Measurement and Determination of Zernike coefficients has been a significant effort of many. However the use of this data has generally been limited to matching lenses or picking best fit lense pairs. We will use wavefront aberration data collected using the Litel InspecStep in-situ Interferometer as input data for Prolith/3D to model and predict pattern placement errors and intrafield overlay variation. Experiment data will be collected and compared to the simulated predictions.

The concept of Mask Error Enhancement Factor (MEEF) is introduced its impact on the future of semiconductor fabrication is explained. The effects of numerical aperture, print bias, and exposure conditions of MEEF are explored using both theoretical and experimental methods.

The AMAG comprised of representatives from International SEMATECH consortium member companies and the National Institute of Standards and Technology have joined to develop a new unified specification for an advanced scanning electron microscope critical dimension measurement instrument (CD-SEM). This paper describes the result of an effort to benchmark six CD-SEM instruments according to this specification.

As advanced source illumination options become available for production implementation, at the 150 nm and 130 nm technology nodes, non-linear effects are introduced in the design shrink- path. In previous technologies, in particular 250 and 180 nm, partial coherence settings are used as a method to control mono- dimensional CD variations among features with different pitches. Source optimization becomes a function of the design pattern to be imaged and of the OPC applied to this design. The advent of Quadrupole, Quasar and Custom Illumination Apertures enables and enhances the use of Optical Extension (OE) technique to image features down to half of the KrF wavelength, but imposes stringent geometrical restrictions on the design, which are not currently well understood. Our work presents a novel methodology for analyzing effects of source illumination variations on full chip design layouts, extending and generalizing the concept of process window. By combining a powerful full-chip imaging simulator and an illuminator design tool, a very large parameter space of design geometries can be explored. Comparison between the desired and the actually imaged patterns is performed, yielding statistically significant CD errors. The analysis of this very large number of printability data points, covering the whole design pattern, allows the classification of critical geometries, i.e. the portions of the design which are process window limiting. Our methodology not only provides an illumination optimization tool for the lithographer, but above all, highlights the need for manufacturability verification performed early at the physical layout stage of the semiconductor design process. In particular, a design verification application is shown, where progressive linear shrinks of a given layout are matched against optimal image settings. Quantitative analysis of the resulting pattern failure modes provides a direct feedback for the layout designer.

In previous presentations we have described how conventional product registration does not account for Hidden Product Overlay Errors. The data presented showed that matched and controlled lithocells can still result in 20-30 nm residual overlay error. In the 0.170micrometers and smaller product design rules, there is no longer any tolerance for these errors. The residual overlay can be describe to be a product of lens distortion matching, optical and SEM measurement capability, selection of overlay mark location and pattern specific placement errors. In this paper we extend our initial findings to describe a procedure we have generalized to analyze the signatures of the systematic components of residual product overlay. The remaining systematic errors are deciphered and encoded into the standard run-to-run alignment offset feedback algorithms. The result is a significant reduction in product misalignment. The ramification is the realization of overlay control suitable for sub 0.150 micrometers DRAM volume.

Optical Proximity Correction (OPC) through assisted features in masks is one of the resolution enhancement techniques in advanced optical lithography. When printing sub-wavelength features on a wafer, OPC becomes necessary. Since OPC is process dependent, it is no easy task to find optimized OPC level for specific lithography process with either rule based or model based OPC application. To benefit from OPC in aggressive gate geometry, the level of correction needs to be optimized. We propose a practical method in OPC optimization using a CD-SEM. During the early process development phase, a test mask can be generated with various levels of OPC correction on a typical feature to be monitored during and after process development. A test wafer is the processed using the test mask using pre-determined photo process. A series of SEM images of the OPC feature on the test wafer will be automatically acquired by a CD-SEM. An OPC optimization algorithm will analyze the acquired images and find contour edges of those images. The contours from those images will be then overlaid on top of each other. With ideal feature shape as a reference, the closest contour to the ideal feature represents the optimized OPC among those tested OPC levels. The selected OPC, not only takes into account of optical effect from scanner optics, but also resist related effects. Production masks can then be produced with the selected level of OPC to maximize the benefit. In this paper, we will demonstrate the above- proposed OPC optimization process.

Resolution enhancement techniques and higher NA exposure are employed to meet the lithography requirements imposed by aggressive shrinks to chip feature sizes. For certain critical levels, like storage and isolation patterning of DRAM devices, the capability to exactly reproduce the mask layout is limited. Severe corner rounding and line image shortening can occur. Such phenomena can be significant contributors to side effects like current leakage, inadequate retention time, stress, and perhaps yield loss. Our development work has shown that the use of Serif and Hammerhead structures can improve resolution printing. Moreover, better process latitude and CD control can be achieved. This paper gives an overview of these innovative techniques. It includes the consideration of different design layouts based on simulations, as well as mask making limitations e.g. mask inspection capability. The benefits of these techniques are discussed and illustrated with detailed lithographic performance data and SEM pictures.

As technology continues to shrink with tighter design rules, it becomes inevitable for the integrated process to demand a more stringent control over the in-line parameters. For multilevel interconnect, each processing step in the formation of every layer of via plug and metal interconnect impacts the overall performance and yield of the silicon wafer. The control of the process thus becomes even more challenging as more layers of interconnect are required to meet the speed performance and density requirements.

As geometries continue to shrink and the equipment is pushed closer to its true limits, overlay and other printing parameters become a larger part of the total budget. Overlay and CD measurements are sampled 'in line' to track and target tools. Adding these parameters to the electrically tested database along with sort data improves yield correlation and failure analysis both during development and in manufacturing. Typically electrical alignment structures such as a resistor divider work well for a few layers but are limited to layers connecting to resistor elements. This paper describes a novel resistor ladder structure that can measure alignment between any 2 conducting layers as well as measure tip pullback, layer to layer patterning impacts, and other characteristics in real device type layouts. Only mask generation and wafer printing capabilities limit the accuracy of the measurement.

A study of both thickness dependent optical and dielectric properties of a low-dielectric constant polycrystalline polymer thin film is investigated. It is demonstrated that the refractive index increase with increasing film thickness, but for thickness < 200 nm, abnormal decrease of the refractive index with increasing film thickness is observed. It is also found that the dielectric strength has a strong dependance on film thickness, which decrease with increasing film thickness. Optical spectroscopy and current ramping voltage test are involved to investigate thickness dependence of optical and dielectric properties. The observations are discussed in terms of our and other models for film thickness dependent of dielectric strength as well as refractive index.

With the exponential increase in device densities and operating speeds, further improvements in chip performance are more difficult to achieve due to the physical limitations of conventional interconnects. Optical interconnects provide one of the solutions to continue improving performance of future technologies. Unlike other optical systems, the prosed approach requires minimal changes in conventional fabrication processes. Other major barriers to industry-wide acceptance are perceived limitations in performance. In this research, models have been developed to show that the performance of optical interconnects is a strong function of technology and layout.

Recently experimental evidence for static spin/charge order or stripes in Mn-Ni and Cu-oxides has been emerging. One may view the stripe order in doped antiferromagnets asa new 'nanophase'.

The effectiveness of a platform development approach for next general logic technologies is discussed. Of the critical material changes that are being considered for the 0.1 micrometers technology generation and beyond, high k gate dielectrics will be driven by low power technology needs while low k and SOI technology enhancements will be driven by high performance technology requirements along with other technology 'extras'. The result is less overlap in technology requirements for low power logic technology relative to high performance logic technology at the immediate technology generation in question, but increased early learning for the following generation.

Via fill and intervia coverage of AR5 and AR7 anti-reflectants were measured for 608nm deep vias in thermal oxide. Fitting functions were found which gave god agreement with experimental data. The most important factors were AR thickness, via duty ratio and via width. The importance of these factors was different for via fill and intervia coverage, and for AR5 and AR7. AR7 was found to fill a range of vias to a depth of 25 percent to 50 percent, suitable for a partial planarization approach to dual damascene fabrication. Planarization was shown to be relatively insensitive to several coat process variations, but sensitive to solution surface tension.

The comparative analysis of the dry etching of FLARE 2.0 and a- C:F, which represent two different depositions techniques of organic low-k polymers was investigated. In our damascene architecture, the etchings to player or hard-mask of both SIOF; SiO₂ was studied. Especially, the SiOF providing lower dielectric constant than SIO₂ would reduce entire effective dielectric constant. The etch rate and etching rate selectivity was optimized by changing content ratio between CHF₃, N₂ and O₂. Furthermore, the bias power, RF power; and gas flows were changed to control the etch profile. The SEM result showed that the better etch profile can be obtained at higher bias power. There were some deviation between etching rate of blanket with the case of patterned wafer. The distribution density of the reactant etching gas in sub-um gap different from blanket surface of wafer was major dynamics. Due to this phenomena, the etching rate became nonlinear function of process time T_etch in the trenches/vias with smaller dimension.

A new model for the rate of material removal in chemical mechanical polishing has been developed. It is, for the first time, demonstrated that there is a critical pressure resulted from the interaction between the slurry and the pad. The critical pressure can either be positive upward exerted on the wafer or negative downward sucking on the wafer. Moreover, the critical pressure is shown to depend on the relative velocity between the wafer and the pad, the viscosity of the slurry and the pad surface. The removal rate at zero applied load can be significant in the case of a negative downward critical pressure. On the other hand, in the case of a positive upward critical pressure, the CMP removal will not occur until the applied load becomes larger than the critical one.

We have developed a 50 angstrom IMP Ti film for 300mm liner application. The process development was done on 300mm iLB Endura Platform, which combines the high bottom coverage and scalability of IMP Ti with the conformality of the CVD TXZ TiN process to address low contact resistance and good adhesion for W and Al application. The IMP technology has an advantage of significant improving the step coverage but has a limitation on obtaining a good film uniformity due to high pressure operation and coil sputtering non-uniformity. ICE technology was used to improve the coil sputtering non-uniformity and film uniformity was improved to approximately 4 percent. Further investigation revealed that the target to substrate spacing has a direct effect on film uniformity. It was found that there is optimum spacing for which great film uniformity can be achieved. The coil position between the target and substrate plays an important role as well. 1000 wafer marathon was performed and average 1.26 percent thickness uniformity was achieved. Thickness was 51 angstrom with 0.4 percent wafer to wafer repeatability.

The need for higher interconnect current densities has been increasing rapidly for advanced integrated circuits. Cu interconnects have emerged as viable candidates to replace Aluminium due to the lower sheet resistivity and increased electro migration lifetime of Cu. Previously, we had reported the use of the isothermal test as a WLR monitor for detecting process defects such as voids in the Aluminium interconnects. This paper further extends the application of the isothermal test methodology for detecting and characterizing process defects in Cu interconnect technology. Package electro migration test are time consuming and may be impractical in detecting process defects in a timely manner. Isothermal test, on the other hand, can be effectively used as a fast WLR process monitor. This paper reports the influence of direction of test current as well as different types of test structures, such as a single level NIST structure and a via chain structure and a via chain structure, on the isothermal test results for Cu interconnects. The isothermal test data has been shown to be helpful in evaluating the location and severity of the process defects through a proper choice of test structures. Joule heating due to high current density is found to be the major driving force for the sensitivity of isothermal test failures. A good correlation is also seen with the package electro migration data. A simple wafer level isothermal test has thus been successfully demonstrated as a reliability tool for process monitoring in Cu VLSI interconnects.

One of the challenges of scaling Shallow Trench Isolation (STI) is controlling the Vt and Idsat of narrow devices. In this paper, we show that Idsat of narrow devices is strongly affected by changes in mobility due to stress from the trench edge. We also show that Vt and leakage of narrow devices is controlled by dopant re-distribution in the channel caused by TED and boron segregation to the trench sidewalls.

Bitmap and electrical microprobe techniques were employed to detect and isolate NMOS gate depletion within the SRAM cells of our 0.20micrometers Complementary Poly CMOS process. This gate depletion problem led to a 3X drop-off in device drive current and about a 300mV increase in threshold voltage. These shifts in device performance produced massive circuit failures within memory circuits and zero yield at wafer probe. Experiments were performed towards conclusively identifying and resolving this gate depletion failure mechanism. Several process modifications were implemented towards eliminating the NMOS gate depletion problem without compromising our margin against PMOS boron penetration. These process improvements led to dramatic increases in probe yield.

A method has been developed by which, after removal of the bulk silicon in a substrate transfer process, the backside of a wafer can be processed with the same lithography as the front side of the wafer. To achieve an accurate front-to-backwafer alignment accuracy, mirror symmetric alignment markers for an ASML PAS5000 waferstepper have been developed and applied in a Silicon-on- Anything process. In this manner minimum dimension low-ohmic contacts were fabricated on the backwafer. The mirror symmetric alignment markers are used in combination with standard overlay test procedures to characterize the front-to backwafer overlay accuracy. The measured overlay errors are divided up in non- mirror symmetric lens distortions and wafer distortion as a result of the substrate transfer process. The practical minimum device feature that can be realized on the backwafer is limited to 0.9-1.2 micrometers as a result of front-to-backwafer overlay errors.

A systematic simulation-based study on scaling gate oxide thickness and the source-drain extension junction dept of r25 nm MOSFET devices is presented. The target 25 nm MOSFETs were obtained from CMOS technologies with gate lengths 40, 50, and 60 nm and the corresponding source-drain extension junction depths of 14, 20, and 26 nm respectively. Each technology was separately optimized for each value of equivalent gate oxide thickness 1, 1.5 and 2 nm to achieve off-state leakage current <EQ 10 nA/micrometers for 25 nm devices. The simulate device characteristics show that for a target value of off-state leakage current, the magnitude of threshold voltage, sub-threshold slope, and the drain-induced barrier lowering increases while the magnitude of drive current decrease with the increase of gate oxide thickness. On the other hand, the variation in the magnitude of threshold voltage, sub-threshold slope, drain-induced barrier lowering, and the drive current for the similar devices is insignificant within the range of source-drain extension junction depth, 14-26 nm, used in this study. It is also found that the gate delay for 25 nm devices increases significantly with the increase of source- drain extension junction depth. This study shows that the requirements for scaling gate oxide thickness and the source- drain extension junction depth for high performance 25 nm MOSFETs are <EQ 1.5 nm and 15 nm respectively.

The electrical characteristics of NMOS capacitors fabricated using high quality, ultra-thin SiO₂, grown by in-situ steam generation (SSG) in a rapid thermal processing system, and a clustered amorphous SI gate electrode is reported. The results show that, in addition to the enhanced growth rate of ISSG oxides, the lower stress-induced leakage current and significantly improved reliability of ISSG SiO₂ such as a longer time-to-breakdown characteristics, as compared to SiO_{2, such as a longer time-to-breakdown under a constant voltage stress and larger charge-to-breakdown characteristics, as compared to SiO(subscript 2} of similar equivalent oxide thickness grown by rapid thermal oxidation (RTO). In addition, it is also found that the reliability of ISSG oxide is considerably improved as the H₂ percentage increases. The result of Fourier- transformed IR spectroscopy indicates that ISSG oxides exhibit lower compressive strain than RTO oxides. Such appreciably improved reliability of ISSG oxide and reduced compressive strain may be explained by the reduction of defects within the structural transition layer between SiO₂ and Si substrate, such as weak Si-Si bonds and strained Si-O bonds, by highly reactive oxygen atom s which are hypothesized to be dissociated from the molecular oxygen due to the presence of hydrogen.

The electrical behavior of metal-semiconductor-metal (MSM) Schottky barrier photodiode structures is analyzed by means of current-voltage (I-V) measurements at different temperatures. The reverse characteristics of the Schottky contact are examined by taking into account the barrier height dependence on the electric field and tunneling through the barrier. It is shown that, under these conditions the I-V measurements can be used as a fast and simple method to evaluate the barrier height, saturation current density and junction ideal factor of the MSM-photodiode Schottky contact. The results are well consistent with experiment.

In this paper we describe a non-destructive technique that characterizes Silicon-On-Insulator (SOI) wafers. With this technique, the thickness of the crystalline silicon and BOX layers, as well as the thickness of the native oxide that naturally forms on SOI are determined. Additionally the degree of smoothness of SOI interfaces are measured. The spectra of optical constant, n and k, of the BOX are also determined. The thicknesses, n and k spectra, and interface roughness are determined simultaneously by analyzing broad-band reflectance with the Forouhi-Bloomer equations for n and k. The reflectance measurement is based on all-reflective optics to generale a highest possible signal-to-noise ratio over the entire measured wavelength range. The total measurement time is about 1 second. We show that the result obtained with the present technique are in excellent agreement with cross-section TEM.

For flexible structuring of a great variety of materials such as polymers ceramics and glass materials, excimer laser radiation has turned out to be a particularly appropriate tool. The excimer laser etching enables the manufacturing of micro-holes and grooves in the micrometer range, as well as the production of complex 3D topographies. In this paper, the surface characteristics of polymer and glass are compared after been etched by 308nm and 197nm UV excimer lasers, the results show that the use of ArF laser allows processing a surface quality close to that of the optics and fabricating ridges about 2micrometers - width. Finally, a rotational mask system is proposed to generate Fresnel lens.

SEMICONDUCTOR300 was the first pilot production facility for 300mm wafers in the world. This company, a joint venture between Infineon Technologies Motorola, started in early 1998 to develop processes and manufacture products using 300mm wafer tool set. The lithography tools include I-line steppers, as I-line scanner, a DUV stepper, and DUV scanners. All of these exposure tools are running in-line with a photoresist coat and develop track. The lithography tools are used to build 64Mb DRAM devices and aggressive test vehicles with design rules of 0.25 micrometers and below, in sufficient quantity to be able to assess the tool readiness. This paper present the history of technical improvements and roadblocks that have occurred on the 300mm lithography tool set since the start-up, and describe a methodology used to assess the tool performance.

Photoresist coating process for IC device manufacturing requires correct target thickness, good uniformity and low defect density. For thick resist films used for Ion Implant, Top Metal layer and/or Pad masks, resist beads built up around the side edges and on top of wafer within 0-3 mm approximately from edges will need to be removed to eliminate defects during ion implantation and etch operations. The conventional method o f using solvent dispenses and optical exposure for edgebead removal does not necessarily solve this problem for resist thickness greater than 1.5 micron. For solvent EBR application, most resist track systems have both top and bottom dispenses nozzles for wafer edge cleaning. However, due to the high risk of unwanted EBR solvent splashes with top EBR nozzle onto wafer surface, which will destroy resist pattern resulting in yield loss, opt EBR solvent application is usually not used. Optical exposure system for wafer edges on the track equipment does not have enough power to completely expose thick photoresist film within a reasonable time for throughput requirement. Hence, the use of optical and backside EBRs only will result in incomplete resist edgebead removal. In this paper, we will describe a new top rinse nozzle design and a combined process of top and bottom EBRs to provide adequate and efficient resist removal around wafer edges for thick photoresist films. A low cost and easy modification to the existing standard to rinse nozzle fora TEL Mark 7 track system was done to provide efficient to solvent EBR application and to avoid solvent splash defects. The low angle to top rinse nozzle below 20 degrees was found to be important in reducing solvent droplet defects. The low angle of top rinse nozzle below 20 degrees was found to be important in reducing solvent droplet defects. Finally, a defect comparison study using KLS2132 will show a lower defect level for the modified top rinse nozzle than the standard one. Qualitative images of wafer edge cleanliness will be shown for resist thickness at 1.5, 1.8 and 2.5 microns using this new nozzle modification.

A novel technique - N₂ ion implant followed by vertical high pressure O₂ re-oxidation in a furnace, capable of growing oxides of multiple thickness is presented. It is observed that the oxidation rate can be well modulated by varying the N₂ I/I dose, and VHP O₂ re-oxidation provides enhanced oxide growth rate and controls the nitrogen profile in the film, as compared to RTO or furnace O₂ re-oxidation. Therefore, more than 500 percent differential oxide growth rate can be realized by using N₂ I/I and VHP O₂ re-oxidation. In addition, post-implant RTA N₂ anneal is found to improve the channel carrier and alter the flat-band and threshold voltages without increasing the oxide thickness.

We report the recent progress and issues related to low-k dielectric etch using TEL Unity II tools. Various low-films have been evaluated in terms of etch and post-etch ash. Inorganic and Organo-Silicate Glass films can be etched by modified oxide etch chemistry. In contrast, organic films are etched by non- fluorocarbon chemistry. Although etching the low-k film sis not so difficult, the concern in the damage caused by etch or ash. FTIR, XPS, Secondary Ion Mass Spectroscopy analysis and capacitance measurement suggest that little impact has been induced on the films during etch and properly controlled in-situ ash. Finally, we introduce the dual damascene scheme with spin-on bi-layer hardmask with SiLK.

In order to increase the radial homogeneity of resistivity and life-time of minority carriers of monocrystalline silicon doped by neutron-transmutation it is suggested an approach based on the accounting of geometric size of samples and conditions of post- irradiation thermal processing. The studies have shown that reduction of thickness of wafers leads to improvement of homogeneity, and that life-time of minority carries strongly depends on the cooling rate, increasing with decrease of this rate. Here the surface of silicon wafers with mechanical imperfections act as efficient gutters for recombination-active centers, where thermally stimulated diffusion of defects from the bulk to the surface plays crucial role, requiring longer thermal processing for thicker wafers.

The work contains results of investigations on the phenomena of the electron emission in thin oxide layers (ITO) in which internal electric field has been generated. Two conducting and transparent films of In₂O₃:Sn were evaporated on both sides of a microscopic cover glass. One film of the thickness 10 divided by 20nm was the emitting surface. The other, of thickness 1 micrometers , was polarized in order to create an internal field. Applying a negative voltage U_pol to field electrode created the internal electric field. The investigations were performed in the vacuum of the order 10^-6Pa. As a result of applying U_pol and illumination, electrons are released and enter electron multiplier. The electrons create voltage pulses in the multiplier, which are recorded in the multichannel pulse amplitude analyzer. The pulses are recorded in channels of the pulse analyzer, creating so-called voltage pulse amplitude spectrum. The amplitude spectra were measured for unilluminated samples and illuminated by a quartz lamp. With increasing U_pol and after illumination the count frequency of pulses grows monotonically. At low U_pol the increase is linear. At higher U_pol this dependence is exponential. This may be evidence that the electric field initiates electron collisions, which proceed according to impact ionization mechanism. Photoinduced optical second harmonic has been also observed in these films. Theoretical calculations have shown that SnO₄ tetrehedral interacting with SiO₄ clusters of the glass substrate play central role in observed nonlinear photoinduced changes.

IN the present work are investigated the current-volt characteristics of the symmetric n⁺(a-Si:H)-i(a-Si:H)- n⁺(a-Si:H), n⁺(a-Si:H)-i(a-Si_1-xGe_x:H)- n⁺(a-Si:H)-structures, where i-a-Si_1-xGe_x:H is x equals 0.57, Eg equals 1.35 eV, and n⁺(a-Si:H)-i(a-Si_1-xGe_x:H)- n⁺(a-Si:H)-structures with varyband i(a-Si_1-xGe_x:H) layer, where E_g of the layer varied from E_g(a-Si:H) equals 1.75 eV up to E_g(a-Si_xGe_x:H) equals 1.35eV. The varyband layer in n⁺-i-n⁺- structure creates the internal built-in field E_builtequals (Delta) (Epsilon) _c/(q*(Delta) x), which is the additional internal built-in potential for the electrons E_built equals 0.32 eV. Additional increase of the electrical field, for the account E_built, in varyband layers results in increase of the currents. It corresponds to more increase of injected current in the varyband structure in comparison with non varyband at V > 0.15 Volt. In the field of voltage V > 0.5-1.0 Volt the dependence J-V^m for all n⁺-i-n⁺-structures is executed, so for the symmetric structure m equals 2.8, for the varyband structure at the direct displacement m equals 3.6 and at return m equals 1.3.

This paper examines the experimental researches of structure defect generation in (Cd, Hg)Te epitaxial layers on CdTe substrates and CdTe mono-crystals after pulse laser treatment and the influence of these defects on mechanical, optical and galvano-magnetic properties of the samples. In the experiments we used the ruby laser radiation with energy density changed in the range 1.5-15 J/cm². The duration of laser pulses was about 1.5 ms. Changes in the chemical composition of the irradiated surface have been analyzed by the Auger electron spectroscopy. The zones with increased defect concentration were determined by the method of the selective chemical etching. It has been determined that the pulse laser processing results in both the essential redistribution of the component concentration and generation of the point and extended defects in near-surface crystal layers excited by laser irradiation. After the laser irradiation of the samples the redistribution of the intensity of the luminescence bands and emergence of a new band were observed over the band 840 nm at the temperature of samples about 4.2 K. The essential growth of the spectral band intensity with a maximum within the band 875-885 nm at T equals K has been observed as well.

Microdisplay-based imaging system are quickly becoming very important. A light valve based on a GXGA microdisplay with 5 megapixels is targeted. The pixel pitch is 15 micrometers , leading to an active display area of 38.4 by 30.72 mm. Both the design and the fabrication of such a large die have presented several challenges. This paper describes the design of reticles for GXGA resolution with on-chip drivers. The chip size associated with this resolution e4xceeds the available reticle size. Stitching is used for the processing of large x-Si backplanes. The reticle set is also suitable for GXGA and XGAp resolutions with drivers. The front-end layers are implemented in a standard double metal 0.7micrometers CMOS technology extended with minimal adaptations. The back-end comprises advanced sub-halfmicron processing steps: two metallization layers with a 500nm-feature size for the light shielding function resp. mirroring function.

The purpose of this paper is to present a novel charge-free processing method which could be integrated for future generation feature production. The source reported here is a surface- reflection neutralization based inductively coupled plasma sources. Experiments and simulations how that his source can produce enough low energy fast neutrals for ashing applications. The cleaning efficiency and stripping rates are characterized as a function of operating parameters. Measurements using a heat flux and momentum analyzer show the neutral flux is on the order 10¹⁵ cm^-2s^-1 and the neutral energy is tunable between 3-6 eV. Process damage assessment by various plasma processes, such as continuous vs. pulsed plasmas, has been included in this paper. These results demonstrate this source is promising for development soft-landing steps suitable for fragile features.

In our work, fluorinated amorphous carbon films (a-C:F) was deposited by PECVD. The amorphous carbon films (a-C:F) with low dielectric constant (K-2.3), thermal stability and acceptable adhesion to cap-layer such as SiOF was obtained by optimum of content ration between carbon with fluorine and adding few SiH₄ for improvement of adhesion. The etching profile with high aspect ratio and etching selection ration more than 50 (a- C:F/SiOF) were obtained by etching gas of N₂+O₂. Furthermore, we demonstrated the technology of electroplating copper in trenches or vias as small as 0.15 micrometers , 6:1 AR. The wetting agent system was consisted of mainly two molecular weights polyethylene glycols (PEG). The small molecular weight PEG with better diffusion ability for reducing the surface tension and the larger PEG enhancing grain growth control was proposed for the first time to wet the inner portion of the sub- 150 nm damascene feature. The leveling agent system was mainly heterocyclic compound contained N, S atoms offering sufficient activation over-potential and selective inhibition gradient.