Copper (Cu) will be used to replace aluminum in the next generation metallization due to its low resistivity and high electromigration resistance. However, copper is a fast diffuser in silicon and silicon dioxide, and it is detrimental to the devices if it gets into the active region. We have investigated several approaches to contaminating with Cu the back surface of a fully processed BiCMOS wafer in order to study its effect on devices. In order to estimate the amount of Cu driven to the active region, a simulated drive-in diffusion experiment is used. Vapor Phase Decomposition--Atomic Absorption Spectrometry is used to measure Cu on the front surface of the wafer after annealing. In a fully processed BiCMOS wafer, the internal gettering: oxygen precipitation occurs at the initial high temperature process steps. This oxygen precipitation acts as trapping centers and an intrinsic barrier that prevents impurities that may be driven from the back surface of the wafer. The effectiveness of the internal gettering of a simulated BiCMOS processed wafer is measured in comparison to a monitor wafer which has no internal gettering. Electrical measurement shows an increase in the base current in a Gummel Plot measurement of the Bipolar device after Cu contamination. This effect is most visible for a wafer that has been annealed at 550 degree(s)C for 30 minutes.

Dual damascene patterning is essential for the integration of copper into a high performance interconnect, hence the etching process becomes the most important challenge. This paper described the work on the dual damascene etching. The three most common schemes for patterning the dual damascene structure are trench-first, via-first (also known as counter-bore) and self-aligned etchings. Although only self- aligned etching requires the insertion of a stop layer, the stop layer is crucial to all schemes for a better control of the etching uniformity. The impact of using a stop layer with every dual damascene scheme was investigated. Lithography plays an important role in damascene etching. The use of negative-tone photoresist for metal trench masking and the challenge of forming a residue-free damascene structure in the presence of a bottom anti- reflecting coating were discussed.

As the device dimension approaches to subquarter-micron, the scaling of geometry's causes an increase in interconnection resistance and current density. Copper is to replace the widely used aluminum, because of the low resistivity and resistance to electromigration. However due to the difficulty of dry etching of Cu, a damascene process is required, which needs a narrow gap filling process. But the step coverage of conventional sputtering if too poor to fill narrow gaps. Though the reflow process of sputtered Cu films is reported to improve the filling property, it is still difficult to fill high aspect ratio vias/trenches. This paper will discuss the continuous and conformal copper seed layer formation using Ionized Metal Plasma (IMP) technique for high aspect ratio vias, which is one of the key to void free electroplating of copper and for a Metal Organic Chemical Vapor Deposition (MOCVD) Cu gap filling with good adhesion. A copper seed layer of around 150 - 200 nm is deposited by IMP and to be followed by a thicker layer of MOCVD or electroplating. More over excellent bottom and side wall coverage was achieved on a patterned wafer with high aspect ratio vias/trenches. The key challenge here will be good adhesion and step coverage of Cu seed layer with the underlying barrier metal Ta/TaN, which is a good candidate of diffusion barrier for Cu. In overall the sheet resistance, adhesion, step coverage etc. will be discussed in the paper.

We report for the first time the effect of a Cu flash layer sandwiched between copper film and TaN barrier layer on the properties of copper films. The structures studied, including a Cu film deposited by Metal Organic Chemical Vapor Deposition (MOCVD), Cu flash layer and TaN barrier by ionized metal plasma (IMP) technique on Si substrate with SiO₂, were fabricated in a three-in-one system supplied by Applied Materials and characterized by x-ray diffraction, atomic force microscopy, adhesion test and stress measurement. By depositing a Cu flash layer with IMP technique prior to the MOCVD deposition, the properties of the MOCVD Cu films can be significantly improved. The <111> oriented diffraction intensity of the Cu film is found to increase, while the intensity of other direction diffraction <200> to decrease as the thickness of the Cu flash layer is increased. The adhesion strength of the CVD Cu film to the flash layer and TaN barrier metal, determined by scratch test and pull tester, is enhanced as the Cu flash layer becomes thicker. The root mean square roughness and the grain size of CVD Cu film is found sensitive to the Cu flash layer and can be optimized by monitoring the deposition of the Cu flash layer. In addition to these, some other properties of the Cu film and the mechanism for the improvement in the properties are also discussed.

Thick polymer residues were observed in vias after plasma etching (in a CF₄/CHF₃/N₂ atmosphere) and subsequent photoresist strip. It was determined that these hardened residues were caused by the etching of underlying titanium-rich films (such as titanium, titanium nitride, titanium tungsten, and titanium silicide) during the via over etch. Polymer residues were not seen when the underlying film was aluminum or tungsten. In addition, hardened polymer formation was not observed when the total amount of titanium-rich metal being etched was decreased below a certain threshold value. The results of this work indicated that when relatively large amounts of titanium- rich films were etched using standard CF₄/CHF₃/N₂ oxide etch chemistries by, thick polymer residues formed in the vias. Because the residues were metal-rich, they were insensitive to changes in the CF₄/CHF₃ ratio. It was determined that the most straightforward way of eliminating the residues was by using an amine based photoresist strip solvent (EKC 265). However, it was found that the EKC 265 must be properly rinsed in order to achieve acceptable via chain resistance.

Thermal stability is a critical issue for polymer thin films being used as interlevel dielectrics (ILDs) in deep- submicron multilevel interconnection. One of crucial parameters to predict thermal stability is the glass transition temperature (T_g). Unfortunately the glass transition in polymer thin films is still not clearly understood. In this work, a simple model is developed for the thickness dependence of T_g of polymer thin and ultrathin films. It is predicted that T_g of polymer thin films can either be reduced or enhanced in comparison with its bulk values, depending on the polymer-substrate and polymer-surface interactions. In addition, the thickness- dependent T_g of polymer thin films can exhibit a minimum as a function of thickness. Experimental data from technologically important ILD films are obtained to support the theoretical model.

A spiral inductor is integrated into an existing CMOS triple layer backend process. To obtain a high quality factor `Q' for the inductor the existing one micron thick metal 3 process was replaced by a three micron thick metal process. The necessary process modifications to integrate this thicker metal process are presented.

This paper reviews work to integrate Flowfill^TM planarizing dielectric with Forcefill^TM aluminum plug in a 0.5/0.35 micrometers CMOS design. Work to reduce dielectric cracking by modifying the stress of the IMD material is described. The paper discusses liner choice for the Forcefill^TM interconnect and how it can influence lithography accuracy, line resistance and electromigration. The use of via chain resistance as a test to determine the degree of metal hole-fill is described.

The effect of some key variables such as rapid thermal processing (RTP) temperature, substrate cleaning method and capping layers, on cobalt silicide formation has been investigated. The in-situ RF sputter etch is found to give a post RTP2 R_sh that is equivalent to a wet cleaned wafer. The temperature transformation curve of cobalt films, analyzed with R_sh data and XRD, reveal the formation of Co₂Si-CoSi-CoSi₂ phases in that order. The transformation curves of TiN capped films match those of blanket cobalt but the Ti capped films show the CoSi phase to be stable over a broader temperature range. There is no effect of dopants on the final cobalt disilicide R_sh values for either the single of polycrystalline substrates. Controlled oxygen leak studies in the RTP ambient reveal that the R_sh after RTP1 is degraded if a capping layer is not present. Electrical test results confirm the need for capping layers. This is indicated by lower R_sh and R_c values on both n+ and p+ junctions and poly structures. Furthermore the electrical results are comparable for Ti and TiN layers used as the cap films although the R_sh/R_c values are in general lower for the TiN capped films. Poly gate length vs R_sh plots show the extendibility of the capped cobalt silicide process to the 0.18 um node.

A critical aspect of interconnect process development is identifying and eliminating yield impacting defects. A methodology is described which has been implemented at Applied Materials to utilize wafer metrology tools to drive process development for advanced interconnect fabrication. The methodology is based on a patterned wafer inspection tool, the WF736Duo, combined with a high throughput defect- review SEM with automatic defect classification, the SEMVision. This combination is tools facilitates defect sourcing and elimination. The requirements for defect reduction are increased since defects can result from both the levels and the interaction between levels. A full-flow Cu damascene interconnect process is examined from oxide deposition to final electrical test to establish inspection strategies for defect reduction. The inspection points for optimal defect reduction are identified based on e-test determination of yield limiting defects. The WF736 was utilized to capture a wide range of defects at the various processing steps. The progression of the defects is tracked to the final e-test point. This tracking both establishes the key defect types and facilitates defect sourcing. Further, the unique ability of the WF736 to segregate defects during the inspection with no loss in throughput, along with the SEMVision ADC analysis, allowed for faster defect sourcing.

The reduction of chip size by using the stitched word line architecture for the 256 M DRAM design demands a maximum metal sheet resistance of 140 mOhm/sq. To meet this requirement a metal thickness of 380 nm is necessary. Our investigations showed that the lithographic as well as the process window of the metal etch process are significantly widened by using a hardmask for the metal etch. The hardmask deposition doesn't have any detrimental effect on the metal film. Both processes, the mask open etch and the metal etch, can be used to adjust the final metal dimension. The key for saving a high metal short yield is the clean after mask open etch. Because of the absence of resist during the metal etch, the formation of polymer rails along the metal lines is suppressed and the post metal etch clean is no longer necessary. The new metal etch process was checked within volume production of the 64 M DRAM without any yield loss. In addition, several reliability investigations don't show any problems. This hardmask metal etch process has, because of the low resist thickness, a large potential for further shrinking.

The goal of this paper is to understand the optical phenomena at dielectric levels (contact, local interconnect, via and damascene line levels). The purpose is also to quantify the impact of dielectric and resist thickness variations on the CD range with and without Bottom Anti Reflective Coating (BARC). First we will show how all dielectric levels can be reduced to the stack metal/oxide/BARC/resist, and what are the contributions to resist and dielectric thickness range for each levels. Then a simple model will be developed to understand CD variation in this stack: by extending the Perot-Fabry model to the dielectric levels, developed by Brunner for the gate level, we can obtain a simple relation between the CD variation and all parameters (metal, oxide thickness, resist thickness, BARC absorbency). Experimentally CD variations for damascene line level on 0.18 micrometers technology has been measured depending on oxide thickness and resist thickness and can confirm this model. UV5 resist, AR2 BARC from Shipley and Top ARC from JSR have been used for these experiments.

This study will specifically address the results of integrating IMP Ti and MOCVD TiN on a high vacuum system. Results of design of experiments used for process characterization and optimizing device parametric such as contact and via resistance will be discussed, in particular with respect to unlanded via schemes. Finally, Cost of Ownership calculations will be presented in comparison to conventional PVD technologies. In summary, the integration of IMP Ti and MOCVD TiN enables the deposition of a highly cost effective, low resistivity, ultra-thin, and low- temperature liners for sub 0.18 micrometers technology node thereby enabling > 500 MHz microprocessor technology.

The combination of IMP Ti and CVD TiN is well established for use as W-adhesion films for 200 mm wafers. The advantage of this unique PVD/CVD integrated solution provides the superior Ti bottom coverage by IMP Ti and conformal TiN coverage from MOCVD TiN. A 300 mm liner and barrier system with integrated IMP Ti, MOCVD TiN has also been developed on Endura mainframe. Scale-up to 300 mm poses several unique challenges to both CVD and PVD processes. Additionally, since 300 mm processing will likely be implemented at sub 0.18 micrometers mode, ultra-thin liners will be required for superior device performance. This paper discusses the process characterization of the 300 mm IMP Ti and MOCVD TiN for thin films (<200 A Ti and <100 A TiN). The Rs and Rs uniformity of 300 mm IMP Ti and CVD TiN were shown to be comparable with the results achieved for 200 mm. Laser acoustic wave spectrometry measurement of thickness and thickness uniformity of ultra-thin Ti (50 A) and TiN (50 A) will also be presented. Cross sectional TEM study shows superior Ti bottom coverage and conformal TiN coverage were also achieved with the integrated 300 mm IMP Ti/CVD TiN process. Process stability was demonstrated with 250-wafer run. The process results of 300 mm Ar sputtering preclean and degas will also be presented in the paper.

This paper discusses TiCl₄ based PECVD Ti and CVD TiN processes that enable a critical contact technology for cost effective gradient DRAMs. The PECVD Ti contact silicidation process and the CVD TiN barrier process together allow for reliable contact metallization with excellent contact resistance and leakage current performance for aspect ratios >12:1. Such capability has allowed a substantial increase in capacitor height alleviating the need for either a change in the capacitor dielectric as well as allowing the continuation of the bitline over capacitor metallization architecture. In addition, the in-situ silicidation capability of the PECVD Ti process allows for the elimination of the contact silicidation anneal step. When used as the top electrode in Ta₂O₃ based capacitor structures, TiCl₄ based CVD TiN provides for reliable metallization with excellent leakage current performance. Preliminary results show that CVD TiN provides the capability for a complete plug fill with no peeling or cracking.

In many fabs for quarter micron and below technologies a stack consisting of Ti/TiN/AlCu/TiN or Ti/AlCu/TiN is being used for metallization. A new approach for metal stack deposition of 0.25 micrometers and beyond, utilizing hew design rules, has been used for DRAM processes. The novel metal deposition process uses an insitu nitrogen purge directly after deposition of bottom Ti to achieve a passivation of the Ti with a thin nitride before deposition of AlCu. This novel approach has been compared to standard metallization stacks consisting of Ti/AlCu/TiN and Ti/TiN/AlCu/TiN.

The sub-threshold characteristics and the reliability of BJTs, using platinum contact silicide (PtSi) or titanium contact silicide (TiSi₂), are compared and analyzed. During processing, it is observed that the TiSi₂ process produces higher interface state density (D_it) than the PtSi process. The increase in D_it not only leads to a higher base current in the BJTs, but also leads to a lower transconductance for the MOS transistors. The data also show that the impact on NPN and nMOS is more severe than the impact of PNP and pMOS, respectively. This can be explained by the non-symmetric interface state distribution, the re- activation of boron, and/or by substrate trap centers. The amount of interface states produced depends not only on the thickness of the titanium film deposited, but also on the temperature and duration of the titanium silicide process. The electrical data indicates that after all the Back-End- Of-The-Line processing steps, which includes a forming gas anneal, D_it is still higher on wafers with the TiSi₂ transistor's base current increases at different rates between the two processes, but eventually levels off to the same final value. However, the PNP transistor's base current increases at approximately the same rate, but eventually levels off at different final values. These indicate that the TiSi₂ process may have modified the silicon and oxygen dangling bond structure during its high temperature process in addition to removing the hydrogen from the passivated interface states.