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Proceedings of SPIE Volume 3508

Multilevel Interconnect Technology II
Editor(s): Mart Graef; Divyesh N. Patel
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Volume Details

Volume Number: 3508
Date Published: 4 September 1998
Softcover: 25 papers (232) pages
ISBN: 9780819429674

Table of Contents
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Damascene Cu-interconnect formation in benzocyclobuten (BCB) film using a novel end-point monitoring technique
Author(s): Yoshihiro Hayashi; Takahiro Onodera; Shinobu Saitoh; Jyun Kawahara
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Integration of hydrogen silsesquioxane into an advanced BiCMOS process
Author(s): Michael Olewine; Ralph N. Wall; Gus J. Colovos
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Effects of post-treatment for low-dielectric hydrogen silsesquioxane (HSQ)
Author(s): Ting-Chang Chang; P. T. Liu; M. F. Chou; Ming-Shih Tsai; Simon M. Sze; Chun-Yen Chang; F. Y. Shih; H. D. Huang
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Control of the interaction of metals with fluorinated silicon oxides
Author(s): Sara E. Kim; Christoph O. Steinbruchel; Atul Kumar; H. Bakhru
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IMP Ta/Cu seed layer technology for high-aspect-ratio via fill by electroplating, and its application to multilevel single-damascene copper interconnects
Author(s): Imran Hashim; Vikram Pavate; Peijun Ding; Barry Chin; Dirk Brown; Takeshi Nogami
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Thin electroless barrier for copper films
Author(s): Sergey D. Lopatin; Yosi Y. Shacham-Diamand; Valery M. Dubin; Yoon So Kim; P. K. Vasudev
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Improved post-etch cleaning of dual-damascene system for 0.18-um technology
Author(s): Didier Louis; Catherine Peyne; Emile Lajoinie; B. Vallesi; David J. Maloney; Shihying Lee
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Characterization of pattern density and the metal stack composition on chlorine residues from the metal etch process
Author(s): Sang Yee Loong; Hian Kee Lee; Mei-Sheng Zhou; Lap Hung Chan; Vayalakkara Premachandran
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Post-etching polymer removal in sub-half-micron device technology
Author(s): Simon Y. M. Chooi; Zainab Ismail; Ping-Yu Ee; Mei-Sheng Zhou
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Titanium silicide etching in sub-half-micron device technology
Author(s): Simon Y. M. Chooi; Vincent K.T. Sih; Soh Yun Siah; Zainab Ismail; Mei-Sheng Zhou
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Etching of dual-damascene oxide structures in a medium-density oxide etch reactor
Author(s): Eric Wagganer; George Mueller; Stephen F. Clark; Kenneth J. Newton
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Novel two-step AI CMP process for overcoming pattern geometry effects
Author(s): Ming-Shih Tsai; Jias-Sheng Lin; Bau-Tong Dai
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Introduction to 300-mm/0.18-um to 0.13-um clean CMP system
Author(s): Manabu Tsujimura
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Chemical mechanical polishing: future processes require CMP tool flexibility
Author(s): F. A. Tony Schraub; John Boyd; Jim Valentine; John Curry
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Copper post-CMP cleaning process on a dry-in/dry-out tool
Author(s): Sanjay Basak; Malcolm Grief; Anand Gupta; Krishna Murella; Barrie VanDevender
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Novel AlCu: fill process for via applications
Author(s): Hans Helneder; Manfred Schneegans; K. Schober; Hans-Joachim Barth; U. Richter; G. Scheinbacher
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Explosive phenomenon of AlCu/TiN and W-plugs multilevel interconnect system
Author(s): J. D. Yang; Chuan-Chieh A. Lin; Anthony Yen; Sen-Fu Chen; Chao-Hsin Chang; Jie-Shin Wu; J. R. Wu
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Applications of Forcefill aluminum for contact and via metallization
Author(s): Juergen Foerster; Werner K. Robl; Norbert Rausch; Manfred Frank; D. Butler; Paul Rich; J. Marktanner
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0.50-um pitch metal integration in 0.18-um technology
Author(s): Jeffrey R. D. DeBord; Vidyasagar Jayaraman; Melissa M. Hewson; Wei W. Lee; John Robert Ilzhoefer
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Integration of a W-plug in an Al-based metallization scheme for 0.25-um IC technology
Author(s): Samit S. Sengupta; Subhas Bothra
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Inorganic bottom ARC SiOxNy for interconnection levels on 0.18-um technology
Author(s): Yorick Trouiller; N. Buffet; Thierry Mourier; Yveline Gobil; Patrick Schiavone; Yves Quere
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Microprocessor technology challenges through the next decade
Author(s): George E. Sery
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Copper chip technology
Author(s): Daniel C. Edelstein
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Foundry technology trend
Author(s): Jack Y. C. Sun
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Equipment challenges for a total material system change: enabling device manufacturing at 130 nm and below
Author(s): Alain S. Harrus; John Kelly; Ronald A. Powell
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