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Proceedings of SPIE Volume 3506

Microelectronic Device Technology II
Editor(s): David Burnett; Dirk Wristers; Toshiaki Tsuchiya
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Volume Details

Volume Number: 3506
Date Published: 4 September 1998
Softcover: 40 papers (364) pages
ISBN: 9780819429650

Table of Contents
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Remote plasma nitrided oxides for ultrathin gate dielectric applications
Author(s): Sunil Hattangady; D. T. Grider; Robert Kraft; Wei-Tsun Shiau; Monte A. Douglas; P. Nicollian; Mark Rodder; George A. Brown; Amitava Chatterjee; Jerry C. Hu; S. Aur; H.-L. Tsai; R. A. Chapman; R. H. Eklund; Ih-Chin Chen; Mike F. Pas
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Advanced gate technology for sub-0.25-um CMOSFETs
Author(s): Tsu-Jae King
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Feasibility study to determine the suitability of using TiN/W and Si1-xGex as alternative gate materials for sub-0.1-um gate-length PMOS devices
Author(s): Suhail S. Murtaza; Jerry C. Hu; Sreenath Unnikrishnan; Mark Rodder; Ih-Chin Chen
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FRAM technologies compatible with 0.5-um CMOS logics
Author(s): Yuji Furumura; Tatsuya Yamazaki; Mitsuhiro Nakamura; Ken-ichi Inoue; Hisashi Miyazawa; Naoya Sashida; Rei Satomi; Yoshikazu Katoh; Souichirou Ozawa; Kazuaki Takai; Hideyuki Noshiro; Rika Shinohara; Yoshiroh Obata; Andrew Kerry; Kouji Tani; Sinji Nakashima; Tetsuya Nakajima; Masahiko Imai; Tohru Takesima; Toshiyuki Teramoto; Chikai Ohono; Moritaka Nakamura; Takayuki Murakami
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High-k scaling for gate insulators: an insightful study
Author(s): Srinath Krishnan; Geoffrey C. Yeap; Bin Yu; Qi Xiang; Ming-Ren Lin
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Laser thermal processing for shallow junction and silicide formation
Author(s): Somit Talwar; Gaurav Verma; Kurt H. Weiner; Carol Gelatos
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Shallow p-type source/drain extension formation using B2H6 plasma doping for deep submicron CMOS
Author(s): Jerry C. Hu; Robert Kraft; Mark Rodder; Ih-Chin Chen
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Process window characterization of RTA source/drain anneal
Author(s): Ravindra M. Kapre; Stephanie Yoshikawa; Wei-Jen Hsia
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Source/drain formation using cobalt silicide as diffusion source for deep submicron nMOS
Author(s): Jerry C. Hu; Qi-Zhong Hong; Jorge A. Kittl; M. Rodder; Ih-Chin Chen
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Self-aligned silicide process technology for sub-0.25-um geometries
Author(s): Ted Regan White; Dave Kolar; Mohamed Jahanbani; Larry E. Frisa; Rajan Nagabushnam; Harry Chuang; Paul Tsui; Jeff Cope; Larry Pulvirent; Scott Bolton
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Evaluation of Mo-doped Ti salicide process for sub-0.18-um CMOS
Author(s): Chih-Ping Chao; Jorge A. Kittl; Qi-Zhong Hong; Wei-Tsun Shiau; Mark Rodder; Ih-Chin Chen
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Sub-half-micron device fabricated with 2-um generation facilities
Author(s): Kiyoshi Mori
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Manufacturing multilevel metal CMOS with deuterium anneals for improved hot-carrier reliablility
Author(s): Isik C. Kizilyalli; G. Abeln; Zhi Chen; Gary R. Weber; F. Register; Edward B. Harris; Sundar Chetlur; G. S. Higashi; M. Schofieled; Sidhartha Sen; B. Kotzias; Pradip K. Roy; Joseph W. Lyding; Karl Hess
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Improving manufacturability of an rf graded channel CMOS process for wireless applications
Author(s): Daniel J. Lamey; Troy Mackie; Han-Bin Liang; Jun Ma; Georges Robert; Craig Jasper; David Ngo; Ken Papworth; Sunny Cheng; Christy Wilcock; Rosemary Gurrola; Edward Spears; Bruce Yeung
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Optimized shallow trench isolation for sub-0.18-um ASIC technologies
Author(s): Faran Nouri; Olivier Laparra; Harlan Sur; Samar K. Saha; Dipankar Pramanik; Martin Manley
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Performance, standby power, and manufacturability trade-off in transistor design consideration for 0.25-um technology
Author(s): Navakanta Bhat; Harry Chuang; Paul Tsui; R. Woodruff; John Grant; R. Kruth; Asanga H. Perera; Stephen Poon; Sean Collins; D. Dyer; Veena Misra; I. Yang; Suresh Venkatesan; Percy V. Gilbert
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Merged 2.5-V and 3.3-V 0.25-um CMOS technology
Author(s): Isik C. Kizilyalli; Robert Y.S. Huang; D. Hwang; Brittin C. Kane; R. Ashton; S. Kuehne; X. Deng; Michael S. Twiford; E. P. Martin; D. Shuttleworth; K. Wittingham; S. Lytle; Yi Ma; Pradip K. Roy; Leonard J. Olmer; Hem Vaidya; F. Li; X. Li; Eric Persson; A. Massengale; L. Stirling; D. Chesire; K. Steiner; Rafael N. Barba; Morgan J. Thoma; William T. Cochran
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Yield management by threshold voltage adjustment in back-end process
Author(s): Shinya Ito; Ko Noguchi; Tadahiko Horiuchi
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Material study of indium implant under channel doping conditions
Author(s): Jinning Liu; Sandeep Mehta; Sonu L. Daryanani; Che-Hoo Ng
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New process for manufacturing thin SiGe and SiGeC epitaxial films on silicon by ion implantation and excimer laser annealing
Author(s): Pierre Boher; Jean-Louis P. Stehle; Jean-Philippe Piel; Eric Fogarassy
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Impact of silicon-type floating gate on EEPROM performance
Author(s): Karine Ogier-Monnier; Philippe Boivin; Olivier Bonnaud
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Ultrathin film fully depleted CMOS/SIMOX technology with selective CVD tungsten and its application to LSIs
Author(s): Yasuhiro Sato; Toshihiko Kosugi; Hiromu Ishii
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Sub-50-nm PtSi Schottky source/drain MOSFETs
Author(s): Chinlee Wang; John P. Snyder; John R. Tucker
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Prediction of deep submicron CMOS transistor performance and comparison with projected performance trends using tuned simulations
Author(s): S. Sridhar; Chih-Ping Chao; Manoj Mehrotra; Mahalingam Nandakumar; Ih-Chin Chen
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Sub-100-nm and deep sub-100-nm MOS transistor gate patterning
Author(s): Qi Xiang; Subash Gupta; Chris A. Spence; Bhanwar Singh; Geoffrey C. Yeap; Ming-Ren Lin
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Response-surface-based optimization of 0.1-um PMOSFETs with ultrathin gate stack dielectrics
Author(s): Anadi Srivastava; Carlton M. Osburn
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Hot-carrier effects in sub-100-nm gate-length N-MOSFETs with thermal and nitrided oxide thickness down to 1.3 nm
Author(s): Geoffrey C. Yeap; Miryeong Song; Qi Xiang; K. Michael Han; Ming-Ren Lin
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New methodology of simulating pocket-implanted sub-0.18-um CMOS
Author(s): Manoj Mehrotra; Jerry C. Hu; Mahalingam Nandakumar; Amitava Chatterjee; Mark Rodder; Ih-Chin Chen
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Optimum junction-depth design of the S/D extension regions (MDD) for sub-0.18-um CMOS technologies
Author(s): Chih-Ping Chao; Manoj Mehrotra; Ih-Chin Chen
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Parasitic resistance analysis for deep submicron CMOS with inverse modeling
Author(s): Manabu Deura; Seiichiro Yamaguchi; Toshihiro Sugii
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Experimental verification of a new physically based low-energy (<5 keV) ion implant model
Author(s): Borna J. Obradovic; Steven J. Morris; Michael F. Morris; Shiyang Tian; Geng Wang; K. Beardmore; Charles M. Snell; J. Jackson; S. Baummann; Al F. Tasch
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Improved analytic models and efficient parameter extraction for computationally efficient 1D and 2D ion implantation modeling
Author(s): Ganesh Balamurugan; Borna J. Obradovic; Geng Wang; Yidong Chen; Al F. Tasch
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Novel thin epi process for high-speed CB-CMOS
Author(s): Vladimir F. Drobny; Kevin X. Bao
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Production of ohmic contacts to AlxGa1-xAs of the n- and p-type conductivity with surface cleaning in atomic hydrogen
Author(s): A. S. Vishnyakov; Valerii A. Kagadei; N. I. Kozhinova; L. M. Romas; Dmitry I. Proskurovsky
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BJT avalanche breakdown voltage improvement by introduction of a floating p-layer in the epitaxial collector region
Author(s): Thomas Zimmer; M. Ndoye; N. Lewis; J. B. Duluc; Helene Fremont; Jean Paul Dom
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Optimum bandgap profile for a high-efficiency p-i-n a-Si: H solar cell
Author(s): Mohamed Bashir Saleh; Tawfik A. Namour; Ahmed K. Aboul Seoud; Sanaa Moustafa
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Microprocessor technology challenges through the next decade
Author(s): George E. Sery
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Copper chip technology
Author(s): Daniel C. Edelstein
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Foundry technology trend
Author(s): Jack Y. C. Sun
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Equipment challenges for a total material system change: enabling device manufacturing at 130 nm and below
Author(s): Alain S. Harrus; John Kelly; Ronald A. Powell
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