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Proceedings of SPIE Volume 3212

Microelectronic Device Technology
Editor(s): Mark Rodder; Toshiaki Tsuchiya; David Burnett; Dirk Wristers
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Volume Details

Volume Number: 3212
Date Published: 27 August 1997
Softcover: 44 papers (406) pages
ISBN: 9780819426444

Table of Contents
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Statistical analysis of dynamic-random-access-memory data-retention characteristics
Author(s): Atsushi Hiraiwa; Makoto Ogasawara; Nobuyoshi Natsuaki; Yutaka Itoh; Hidetoshi Iwai
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Characterization of Vth fluctuation in 0.15-um n-MOSFETs for gigabit DRAM cell transistors
Author(s): Toshihiko Miyashita; Hiroshi Suzuki; Manabu Kojima; Yasuo Nara; Nobuo Sasaki
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Methods for the design of microelectronic devices and process flows for manufacturability
Author(s): Sharad Saxena; Richard Burch; P. K. Mozumder; Karthik Vasanth; Suraj Rao; Joe Davis; Chenjing Fernando
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Methodology for optimizing transistor performance
Author(s): Whitson G. Waldo
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Device performance and optimization for 5th- and 6th-generation microprocessors
Author(s): Bijnan Bandyopadhyay; Jon Cheek; Robert Dawson; Michael Duane; Jim Fulford; Mark I. Gardner; Fred N. Hause; Bernard Ho; Daniel Kadoch; Raymond Lee; Ming-Yin Hao; Chuck May; Mark Michael; Brad Moore; Deepak Nayak; John L. Nistler; Dirk Wristers
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Surface preparation, growth, and characterization of ultrathin gate oxides for scaled CMOS applications
Author(s): Glen D. Wilk
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Optimization of pre-gate clean technology for a 0.35-um dual-oxide/dual-voltage CMOS process
Author(s): Hunter B. Brugge; Martin P. Karnett; Emmanuel de Muizon; Jingrong Zhou; Allen Page; Landon B. Vines; Bradley J. Haby
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Ultrathin oxide for sub-0.25-um technology in silicon ICs: impact of stacking and nitridation
Author(s): Pradip K. Roy; Yi Ma
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Process optimization of dual-gate CMOS
Author(s): I. Min Liu; Yuh Yue Chen; Chris Connor; Atul B. Joshi; Dim-Lee Kwong
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Quasi-breakdowns in ultrathin dielectrics
Author(s): Byoung Woon Min; Dim-Lee Kwong
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Potential of rf Si-MOS LSI technology
Author(s): Akira Matsuzawa
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Thin-film integration for nanoscale and high-frequency electronics on Si
Author(s): Joy Laskar; Nan Marie Jokerst; N. Evers; C. Chun
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Si selective epitaxial growth technology using UHV-CVD and its application to LSI fabrication
Author(s): Seiichi Shishiguchi; Tomoko Yasunaga; Tohru Aoyama; T. Tatsumi; Shuichi Saito
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Applications of silicon-germanium-carbon in MOS and bipolar transistors
Author(s): Sanjay K. Banerjee
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Strained Si NMOSFET on relaxed Si1-xGex formed by ion implantation of Ge
Author(s): Soji John; Samit K. Ray; Sandeep K. Oswal; Sanjay K. Banerjee
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Shallow source/drain extension formation using antimony and indium pre-amorphization schemes for 0.18- to 0.13-um CMOS technologies
Author(s): Jerry C. Hu; Mark Rodder; Ih-Chin Chen
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Low-energy BF2, BCl2, and BBr2 implants for ultrashallow P+-N junctions
Author(s): S. Raghu Nandan; Vikas Agarwal; Sanjay K. Banerjee
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Impact of nitrogen ion-implantation on deep submicron SALICIDE process
Author(s): Chong Wee Lim; Syamal Lahiri; C. H. Tung; Sang Min Wong; Kong Hean Lee; Harianto Wong; Kin Leong Pey; Lap Hung Chan
Sheet resistance requirements for the source/drain regions of 0.11-um gate length CMOS technology
Author(s): Manoj Mehrotra; Amitava Chatterjee; Ih-Chin Chen
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Scaling self-aligned contacts for 0.25-um and below
Author(s): Asanga H. Perera; Jim R. Pfiester; Tom Lii; Chris Feng; Mousumi Bhat; Thuy Dao; John Molloy; Michael Blackwell; Joe Cecil
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Advantages of SOI technology in low-voltage ULSIs
Author(s): Makoto Yoshimi; Shigeru Kawanaka; Takashi Yamada; Mamoru Terauchi; Tomoaki Shino; Toshiaki Fuse; Yukito Oowaki; Shigeyoshi Watanabe
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Low-threshold 0.6-um MOSFET for low-voltage rf applications
Author(s): Andrej Litwin; Christian Nystroem; Karl Fagerholm
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Design of 0.18-micron NMOSFETs for low-power applications
Author(s): Shamsul A. Khan; Scott A. Hareland; Al F. Tasch; Christine M. Maziar; Peter Zeitzoff
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Prediction of CMOS transistor performance at 0.10-um gate length using tuned simulations
Author(s): S. Sridhar; Manoj Mehrotra; Mark Rodder; Mahalingam Nandakumar; Ih-Chin Chen
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0.18-um gate length CMOS devices with N+ polycide gate for 2.5-V application
Author(s): Jeong Yeol Choi; Eric Zhang; Chung Chyung Han
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Impact of photoresist taper and implant tilt angle on the interwell isolation of subquarter-micron CMOS technologies
Author(s): Percy V. Gilbert; John Grant; Paul Tsui; Charles Fredrick King; William J. Taylor; Karl Wimmer
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Wafer-scale modeling of pattern effect in oxide chemical mechanical polishing
Author(s): Dennis O. Ouma; Brian Stine; Rajesh Divecha; Duane S. Boning; James E. Chung; Gregory B. Shinn; Iqbal Ali; John Clark
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Improvement of edge leakage in PBL-isolated SOI NMOSFETs
Author(s): David Burnett; Mitch Lien; Kelly Baker
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Hot-carrier degradation for deep-submicron N-MOSFETs introduced by back-end processing
Author(s): Donald Y. C. Lie; Wei Xia; Jiro Yota; Atul B. Joshi; R. Zwingman; R. Williams; V. Kerametlian; Dennis Cerney; Byoung Woon Min; Dim-Lee Kwong
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Effect of local interconnect etch-stop layer on channel hot-electron degradation
Author(s): Jon Cheek; Homi E. Nariman; Dirk Wristers; Deepak Nayak; Ming-Yin Hao
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Plasma-induced charging damage in P+-polysilicon PMOSFETs
Author(s): I. Min Liu; Yuh Yue Chen; Atul B. Joshi; Dim-Lee Kwong
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Applicability of RTCVD and LPCVD nitride spacers for sub-0.18-um CMOS technologies
Author(s): Wei-Tsun Shiau; Jerry C. Hu; Mark Rodder; Paul Tiner; Ih-Chin Chen
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Boron segregation in As-implanted Si due to electric field and transient enhanced diffusion
Author(s): Ruey-Dar Chang; P. S. Choi; Dirk Wristers; P. K. Chu; Dim-Lee Kwong
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Nitrogen implantation: reverse short channel effects improvement and its drawbacks
Author(s): Teck Koon Lee; Yiang Aun Nga; Po-Ching Liu; Chock Hing Gan; Yunqiang Zhang
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Tuned MEDICI simulator including inverse short channel effect for sub-0.18-um CMOS technologies
Author(s): Mahalingam Nandakumar; S. Sridhar; Karthik Vasanth; Jerry C. Hu; Wei-Tsun Shiau; P. Mei; Mark Rodder; Ih-Chin Chen
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Computationally efficient ion implantation damage model: modified Kinchin-Pease model
Author(s): Geng Wang; Shiyang Tian; Michael F. Morris; Steven J. Morris; Borna J. Obradovic; Ganesh Balamurugan; Al F. Tasch
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SiGe/Si vertical PMOSFET device design and fabrication
Author(s): Kou Chen Liu; Sandeep K. Oswal; Samit K. Ray; Sanjay K. Banerjee
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Low-energy model for ion implantation of arsenic and boron into (100) single-crystal silicon
Author(s): Borna J. Obradovic; Steven J. Morris; Michael F. Morris; Shiyang Tian; Geng Wang; K. Beardmore; Charles M. Snell; J. Jackson; S. Baummann; Al F. Tasch
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Si1-x-yGexCy channel heterojunction PMOSFETs
Author(s): Soji John; Samit K. Ray; Sandeep K. Oswal; Sanjay K. Banerjee
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Characteristics of BaxSr1-xTiO3 thin films by metallorganic chemical vapor deposition for ultrahigh-density DRAM application
Author(s): Bigang Min; Jaesung Sung Roh; J. Yan; Dim-Lee Kwong
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Constant current-stress-induced breakdown of reoxidized nitrided oxide (ONO) in flash memory devices
Author(s): Cher Liang Cha; Eng Fong Chor; H. Gong; Alex Q. Zhang; Lap Hung Chan; Joseph Xie
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Characterization of polymer formation during SiO2 etching with different fluorocarbon gases (CHF3, CF4, C4F8)
Author(s): Sang Yee Loong; H. P. Lee; Lap Hung Chan; Mei-Sheng Zhou; F. C. Loh; K. L. Tan
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Narrow-channel transistor threshold self-adjustment technique for ULSI with LOCOS isolation
Author(s): Konstantin V. Loiko; Igor V. Peidous; Hok-Min Ho; John F. Bromley-Barratt; Elgin T. Quek; David Hsuan Yu Lim
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Silicon bipolar transistor scaling for advanced BiCMOS SRAM applications
Author(s): H. Tian; Asanga H. Perera; D. O'Meara; H. De; C. K. Subramanian; P. Rehmann; James D. Hayden; Norm Herr

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