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Proceedings of SPIE Volume 2914

High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic
Editor(s): John Schewel; Peter M. Athanas; V. Michael Bove; John Watson
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Softcover $105.00 * $105.00 *

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Volume Details

Volume Number: 2914
Date Published: 21 October 1996
Softcover: 34 papers (364) pages
ISBN: 9780819423160

Table of Contents
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Signed-digit online floating-point arithmetic for FPGAs
Author(s): Atakorn Tangtrakul; Benjamin Yeung; Todd A. Cook
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Design of high-radix digit slices for online computations
Author(s): Alexandre F. Tenca; Milos D. Ercegovac
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Performance evaluation of FPGA implementations of high-speed addition algorithms
Author(s): William W.H. Yu; Shanzhen Xing
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250-MHz correlation using high-performance reconfigurable computing engines
Author(s): Brian Von Herzen
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Implementation of a finite difference method on a custom computing platform
Author(s): Kevin Paar; Peter M. Athanas; Carleen M. Edwards
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User-configurable data acquisition systems
Author(s): Geoffrey Brown
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Internal sorting and FPGA
Author(s): Al Beechick; Steve Casselman; Lynn D. Yarbrough
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Polynomial-transform-based approach to computing 2D DFTs using reconfigurable computers
Author(s): Chris H. Dick; Fred J. Harris
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Configurable adaptive signal processing subsystem for various applications in telemetry, navigation, and telecommunication
Author(s): Henry Chandran
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Dynamic hardware video processing platform
Author(s): Ray Andraka
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DSP filters in FPGAs for image processing applications
Author(s): Brad Taylor
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Image processing using reconfigurable FPGAs
Author(s): Lee Ferguson
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Design tips and experiences in using reconfigurable FLEX logic
Author(s): Peter J. Covert
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Programmable hardware for reconfigurable computing systems
Author(s): Stephen Smith
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Hierarchical decomposition model for reconfigurable architecture
Author(s): Simsek Erdogan; Abdul Wahab
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Review of field-programmable analog arrays
Author(s): Glen Gulak; Dean R. D'Mello
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PCI-based WILDFIRE reconfigurable computing engines
Author(s): Bradley K. Fross; Robert L. Donaldson; Douglas J. Palmer
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Reconfigurable-logic-based fiber channel network card
Author(s): Steve Casselman
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Colt: an experiment in wormhole run-time reconfiguration
Author(s): Ray Bittner; Peter M. Athanas; Mark Musgrove
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Computational acceleration methodologies: advantages of reconfigurable acceleration subsystems
Author(s): Yvon Savaria; Guy Bois; Pierre Popovic; Andrew Wayne
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Malleable architecture generator for FPGA computing
Author(s): Maya Gokhale; James Kaba; Aaron Marks; Jang Kim
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Resource pools: an abstraction for configurable computing codesign
Author(s): James B. Peterson; Peter M. Athanas
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Solving graph problems with dynamic computation structures
Author(s): Jonathan W. Babb; Matthew Frank; Anant Agarwal
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Using reconfigurable hardware to customize memory hierarchies
Author(s): Peixin Zhong; Margaret Martonosi
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Compiling high-level languages for configurable computers: applying lessons from heterogeneous processing
Author(s): Glen E. Weaver; Charles C. Weems; Kathryn S. McKinley
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Rapid prototyping of datapath intensive architectures with HML: an abstract hardware description language
Author(s): Miriam E. Leeser; Shantanu Tarafdar; Yanbing Li
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Codesign and high-performance computing: scenes and crisis
Author(s): Reiner W. Hartenstein; Juergen Becker; Michael Herz; Ulrich Nageldinger
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FPGA applications in digital video systems
Author(s): Bradly K. Fawcett; John Watson
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Application of FPGA technology to performance limitations in radiation therapy
Author(s): John J. DeMarco; J. B. Smathers; Tim D. Solberg; Steve Casselman
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Embedding large multidimensional DSP computations in reconfigurable logic
Author(s): Ayman Elnaggar; Hussein M. Alnuweiri; Mabo Robert Ito
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FPGA-based transformable coprocessor for MPEG video processing
Author(s): Hoi Chow; Hussein M. Alnuweiri
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Guide to using field programmable gate arrays (FPGAs) for application-specific digital signal processing performance
Author(s): Gregory Ray Goslin
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Reconfigurable hardware accelerator for embedded DSP
Author(s): Keith Reeves; Ken Sienski; Calvin Field
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Large-scale logic array computation
Author(s): Norman Margolus
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