Share Email Print
cover

Proceedings of SPIE Volume 2875

Microelectronic Device and Multilevel Interconnection Technology II
Editor(s): Ih-Chin Chen; Nobuo Sasaki; Divyesh N. Patel; Girish A. Dixit
Format Member Price Non-Member Price
Softcover $105.00 * $105.00 *

*Available as a photocopy reprint only. Allow two weeks reprinting time plus standard delivery time. No discounts or returns apply.


Volume Details

Volume Number: 2875
Date Published: 13 September 1996
Softcover: 38 papers (400) pages
ISBN: 9780819422736

Table of Contents
show all abstracts | hide all abstracts
Stability and reliability of fully depleted SOI MOSFETs
Author(s): Toshiaki Tsuchiya
Show Abstract
High-performance metal-gate SOI CMOS fabricated by ultraclean low-temperature process technologies
Author(s): Takeo Ushiki; Yuichi Hirano; Hisayuki Shimada; Tadahiro Ohmi
Show Abstract
Study of integration issues in shallow trench isolation for deep submicron CMOS technologies
Author(s): Amitava Chatterjee; Mark E. Mason; K. Joyner; Daty Rogers; Doug Mercer; John Kuehne; A. L. Esquivel; P. Mei; Suhail S. Murtaza; Kelly J. Taylor; Iqbal Ali; S. Nag; Sean C. O'Brien; S. Ashburn; Ih-Chin Chen
Show Abstract
Trench isolation technology for high-performance complementary bipolar devices
Author(s): Kevin C. Brown; Chris Bracken; Rashid Bashir; Kulwant Egan; Joe DeSantis; Abul Ehsanul Kabir; Wipawan Yindeepol; Joel McGregor; S. J. Prasad; Reda Razouk; Victor V. Boksha; Juan C. Rey
Show Abstract
Key issues in evaluating hot-carrier reliability
Author(s): James E. Chung
Show Abstract
Effect of the pLDD implantation dose on pMOS transistor characteristics
Author(s): Eitan N. Shauly; Richard M. Fastow; Yigal Komem; Itzhak Edrei
Show Abstract
Snap-back temperature dependence for an Epi-CMOS ASIC-process up to 250 degrees C
Author(s): Dirk Uffmann; Christina Ibrom; Joerg Ackermann; Jens Stemmer; Jochen Aderhold
Show Abstract
Digital standard cells and operational amplifiers for operation up to 250 degrees C using low-cost CMOS technology
Author(s): Jens Stemmer; Joerg Ackermann; Dirk Uffmann; Jochen Aderhold
Show Abstract
Reliability scaling in deep submicron MOSFETs
Author(s): Tadahiko Horiuchi; Hiroshi Ito; Naohiko Kimizuka
Show Abstract
Optimizing a manufacturing submicron CMOS process for low-voltage applications
Author(s): Jun Ma; Sunny Cheng; Bob Pryor; Kevin Klein
Show Abstract
Device and process integration for a 0.55-um channel length CMOS device
Author(s): Whitson G. Waldo; Ibrahim Turkman; Rickey Brownson
Show Abstract
Manufacturing sensitivity analysis of a 0.18-micron NMOSFET
Author(s): Darryl Angelo; Scott A. Hareland; Shamsul A. Khan; Khaled Hasnat; Al F. Tasch; Peter Zeitzoff
Show Abstract
High-performance 0.25-um CMOS technology for fast SRAMs
Author(s): James D. Hayden; T. F. McNelly; Asanga H. Perera; Jim R. Pfiester; C. K. Subramanian; Matthew A. Thompson
Show Abstract
Lg=0.25-um CMOS devices with N+-polycide gate for 3.3-V application
Author(s): Jeong Yeol Choi; Zhijian Ma
Show Abstract
Shadowing of lightly doped drain implants due to gate etch profiles and implanter configurations
Author(s): Neil Bryan Henis; David Abercrombie; Rickey Brownson
Show Abstract
Use of elevated source/drain structure in sub-0.1 um NMOSFETs
Author(s): Jay J. Sun; Jiunn-Yann Tsai; Kam F. Yee; Carlton M. Osburn
Show Abstract
Materials and processing issues in the development of N2O/NO-based ultrathin oxynitride gate dielectrics for CMOS ULSI applications
Author(s): Byeong Y. Kim; Dirk Wristers; Dim-Lee Kwong
Show Abstract
Scaling considerations of interpoly oxide-nitride-oxide dielectric for high-density DRAM applications
Author(s): Zhijian Ma; Jeong Yeol Choi; Chuen-Der Lien
Show Abstract
Influence of carbon contamination on ultrathin gate oxide reliability
Author(s): Toshiyuki Iwamoto; Toshiki Miyake; Tadahiro Ohmi
Show Abstract
Computer-aided optimization of ion-implanted charge bump parameters for rf silicon SDR
Author(s): Shankar P. Pati; A. K. Panda
Show Abstract
Gate oxide field design in the sub-10-nm region
Author(s): Katsuhiko Kubota; C. Suzuki; Kosuke Okuyama; N. Suzuki
Show Abstract
Scalability of conventional and sidewall-sealed LOCOS technology for 256-Mbit DRAM array and periphery isolation
Author(s): Mark Rodder; Jeong-Mo Hwang; Ih-Chin Chen
Show Abstract
Pass transistor and isolation design methodology and its implementation for improved manufacturability for 256-Mbit DRAM and beyond
Author(s): Amitava Chatterjee; Mark Rodder; Ih-Chin Chen
Show Abstract
Reflow of Al-Cu by low-temperature germane reactions
Author(s): R. V. Joshi
Show Abstract
Characterization of W CMP processes for 200-mm applications
Author(s): David A. Hansen; J. Sam Luo; John Nguyen; Gregory Fawley; Sue B. Davis; Lucky F. Marty; Fermion Yang
Show Abstract
Integration of ICP high-density plasma CVD with CMP and its effects on planarity for sub-0.5-um CMOS technology
Author(s): Jiro Yota; Maureen R. Brongo; Thomas W. Dyer; Kenneth P. Rafftesaeth; James A. Bondur
Show Abstract
Comparison of spin-on materials in IMD planarization
Author(s): Simon Y. M. Chooi; Chew-Hoe Ang; Jia Zhen Zheng; Lap Hung Chan
Show Abstract
SOG etch-back process induced surface roughness
Author(s): Po-Tao Chu; Sen-Fu Chen; Jie-Shin Wu; Chih-Chien Hung; Ting-Huang Lin; Ying-Chen Chao
Show Abstract
Process integration of TDEAT-based MOCVD TiN as diffusion barrier for advanced metallization
Author(s): Fang Hong Gn; Qiong Li; Lap Hung Chan; Simon Y. M. Chooi
Show Abstract
Submicron metal etch integration study
Author(s): Simon Gonzales; Jesus Quijada; Gordon Grivna
Show Abstract
Effects of process parameters on microloading in subhalf-micron aluminum etching
Author(s): Jongweon Youn; Ki-Soo Shin; Hee Kook Park; Daehee Kim
Show Abstract
Comparison of the Ti/TiN/AlCu/TiN stack with TiN/AlCu/Ti/TiN stack for application in ULSI metallization
Author(s): Satish S. Menon; Ratan K. Choudhury
Show Abstract
Intermetallic compound formation in hot aluminum metallization and its effect on etching and electromigration
Author(s): Lianjun Liu; Dong Lu; Pang Dow Foo; Way Tat Tan; Kurt Kowk; Gang Zou; Man Siu Tse
Show Abstract
Copper metallization for on-chip interconnects
Author(s): A. V. Gelatos; Bich-Yen Nguyen; Kathleen A. Perry; R. Marsh; J. Peschke; Stanley M. Filipiak; Edward O. Travis; Matthew A. Thompson; T. Saaranen; Phil J. Tobin; C. J. Mogab
Show Abstract
Interconnection schemes for parasitics optimization
Author(s): Nicolas Delorme; Marc Belleville; Sylvette Bisotto; Jean Chilo
Show Abstract
Tungsten plug contact and via integration for subhalf-micron technology
Author(s): Harianto Wong; Chetlur S. Sreekanth; Lap Hung Chan
Show Abstract
Structured CVD-silicon carbonitride coatings
Author(s): Alexey G. Varlamov
Show Abstract

© SPIE. Terms of Use
Back to Top