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PROCEEDINGS VOLUME 2636

Microelectronic Device and Multilevel Interconnection Technology
Editor(s): Ih-Chin Chen; Girish A. Dixit; Trung Tri Doan; Nobuo Sasaki

*This item is only available on the SPIE Digital Library.


Volume Details

Volume Number: 2636
Date Published: 15 September 1995

Table of Contents
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Future manufacturing technology in the year 2000
Author(s): Tadahiro Ohmi
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Novel LOCOS isolation process for producing highly reliable oxides
Author(s): Mark I. Gardner; Daniel Kadoch
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Latch-up temperature dependence of majority carrier guard structures up to 250-degrees C
Author(s): Dirk Uffmann; Jens Stemmer; Hans-Ulrich Schroeder; Joerg Ackermann; Jochen Aderhold
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Plasma charging effects on device degradation from via sputter etch
Author(s): Lakshmanna Vishnubhotla; Jamin Michael Ling; Jimmy Huang; Yujen Wu; Greg Smith; Mehdi Zamanian; Fu-Tai Liou; Kaihan A. Ashtiani; M. D. Mc Nicholas
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Dimension-temperature combination scaling for low-temperature 0.1micron CMOS
Author(s): Kazuya Masu; Michio Yokoyama; Kazuo Tsubouchi
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15 ps cryogenic operation of 0.19-um-LG n+ - p+ double-gate SOI CMOS
Author(s): Toshihiro Sugii; Tetsu Tanaka; Hiroshi Horie; Kunihiro Suzuki
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Statistical threshold-voltage variation and its impact on supply-voltage scaling
Author(s): David Burnett; Shih-Wei Sun
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High-frequency BJT-mode operated MOS structure
Author(s): Iulian Gradinariu; Christian Gontrand
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Prediction of 0.18 um CMOS technology performance using tuned device simulation
Author(s): Mahalingam Nandakumar; Mark Rodder; Ih-Chin Chen
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CMOS LDD process with seven masking steps from well to passivation
Author(s): Jeong Yeol Choi; Chung Jen Chien; Chung Chyung Han; Chuen-Der Lien
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Improved figure-of-merit metric for CMOS transistor performance and its application to 0.25 um CMOS technologies
Author(s): Amitava Chatterjee; Mark Rodder; Ih-Chin Chen
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C-V model of the MOS structures with a shallow p-n junction for the electro-physical parameters and profile of the doping determination
Author(s): Mikhail G. Kuznetsov; Alexander A. Kokin; Sergey A. Kokin
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Integration of BaxSr1-xTiO3 thin film for DRAM application
Author(s): Keiichiro Kashihara; Tomonori Okudaira; Yoshikazu Tsunemine; Yoshikazu Ohno; Hiromi Itoh; Tadashi Nishimura; Makoto Hirayama; Tsuyoshi Horikawa; Teruo Shibano; Kazuo Horie
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Optimizing the performance of advanced nonvolatile memories using differentiated cell source and drain implants
Author(s): Martin Duncan; P. Pansana
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Optimization of memory redundancy laser link processing
Author(s): Yunlong Sun; Richard S. Harris; Edward J. Swenson; Craig Hutchens
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Integrity of N2O oxides in WSi2 polycide process
Author(s): Chung Jen Chien; Jeong Yeol Choi; Guo-Qiang Lo; Chuen-Der Lien
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Influence of the TiNx/TiSy/poly-Si gate preparation process on MOS-structure properties and reliability
Author(s): Victor M. Ivkin; Valentin V. Baranov
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N2O-based tunnel oxides
Author(s): Jack C. Lee; Anthony I. Chou; Kafai Lai; Kiran Kumar
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Improved hot-carrier reliability of MOSFET analog performance with NO-Nitrided SiO2 gate dielectrics
Author(s): L. K. Han; Dim-Lee Kwong
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Oxide/nitride stacked layers prepared by in situ rapid-thermal multiprocessing
Author(s): Hai-Hong Wang; L. K. Han; Jason Yan; Dim-Lee Kwong
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Electrical characteristics of n- and p-MOSFETs with N2O-reoxidized NH3-nitrided N2O oxides as gate dielectrics
Author(s): L. K. Han; Hai-Hong Wang; Jason Yan; Jin-ha Kim; G. W. Yoon; Dim-Lee Kwong
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In-line LOCOS active width characterization using surface SEM
Author(s): Sudhir K. Madan; Tom Holloway
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Integral contact process in submicron technology
Author(s): Yu-Hua Lee; Bing-Yue Tsui
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Development and production integration of a planarized AlCu interconnect process for submicron CMOS
Author(s): Kevin C. Brown; Rodney Hill; Krishna Reddy; Kamesh Gadepally
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Formation of TiN films by metal organic chemical vapor deposition using TDEAT
Author(s): Jaegab Lee; Jaeho Kim; Choogsoo Chi; Sangjoon Park; Kyung-Il Lee; Jaejeong Kim
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Parametral dependence of bilevel-interconnect formation in GaAs ICs/MMICs
Author(s): Seema Vinayak; B. K. Sehgal; G. Sai Sarvanan; Sindhu Dayal; D. S. Rawal; Akshay A. Naik; R. Gulati; I. Chandra
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Submicron patterning of AlSiCu/TiN and AlSiCu/TiW films
Author(s): Simon Y. M. Chooi; Fang Hong Gn; Lap Hung Chan
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Comparative study of submicron gap filling and planarization techniques
Author(s): Adriana E. Hass Bar-Ilan; N. Gutmann
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Characterization of SOG (spin on glass) fully etch back process for multilevel interconnection technology
Author(s): Y. C. Huang; Marx Huang; Sen-Fu Chen; C. H. Yu; L. M. Liu; M. S. Lin
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Dependence of MOSFET hot-carrier aging on PECVD oxide process
Author(s): L. K. Han; D. Allman; Dim-Lee Kwong
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Effects of PE-TEOS process on O3-TEOS characteristics and device reliability
Author(s): Syun-Ming Jang; Yu-Min Lin; Peter Lee; L. M. Liu; C. H. Yu; Tan Fu Lei; M. S. Lin
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Modeling limits of multilevel interconnect technology
Author(s): Bibiche Geuskens; Kenneth Rose
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Manufacturing challenges for sub-half micron technologies
Author(s): Fu-Tai Liou
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