Future success in microelectronics will demand rapid innovation, rapid product introduction and ability to react to a change in technological and business climate quickly. These technological advances in integrated electronics will require development of flexible manufacturing technology for VLSI systems. However, the current approach of establishing megafactories for mass manufacturing of chips will lead to a skyrocketing cost of more than 1 billion dollars to establish a factory by the end of this century. This could result in serious attrition of chip manufacturers. We propose new concepts of a programmable micro factory which may be characterized by more economical small scale production, higher flexibility to accommodate many products on several processes, and faster turnaround and learning. In-situ multi-processing equipment where several process steps can be done in sequence may be a key ingredient in this approach. For this environment to be flexible, the equipment must have ability to change processing environment, requiring extensive in-situ measurements and real time control. In-process and end-of-process measurements coupled with rapid learning through expert systems will facilitate faster innovation and better ability to react to a change.

The viability of rapid thermal processing is assessed for the fabrication of extremely shallow emitter-base profiles in bipolar devices. Junctions diffused from polysilicon using either rapid thermal processing (RTP) or conventional furnace drives are characterized using secondary ion mass spectrometry (SIMS). Results are compared to SUPREM III simulations of the diffusion process. Electrical data is compared for npn polysilicon emitter bipolar devices with emitter-base junctions fabricated using either an RTP emitter drive at 10500C or a conventional furnace drive at 9100C. Potential advantages and disadvantages of RTP are discussed including polysilicon/silicon interface control and required temperature uniformity.

Thin film superconductors of Y-Ba-Cu and Yb-Ba-Cu were formed by the pyrolysis of neodecanoate solutions of Y, Yb, Ba and Cu which had been deposited onto <100> SrTiO3 substrates [1]. Rapid thermal annealing, in oxygen, of the as-deposited films produced high T films having superconducting onset temperatures above 90 K and zero resistance at 8g K. Scanning Electron Microscopy (SEM) revealed enhancements in grain growth, compared to furnace annealed films, by a factor of 4. X-ray diffraction analysis showed preferred epitaxial grain growth with the c-axis of the films oriented both perpendicular and parallel to the substrate surface. Separate Rutherford Backscattering Spectrometry (RBS) channeling experiments confirmed the formation of preferred epitaxial grain growth. Film composition was determined by RBS and Inductively Coupled Plasma Emission Spectrometry (ICPES). Selective patterning was accomplished by focused beam exposure of the metal neodecanoate films [2-4]. The exposure rendered the neodecanoate film locally insoluble in xylene, thus permitting selective area patterning prior to pyrolysis. Electron, ion and laser beams were used to pattern films on <100> SrTiO3. The finest lines, approximately 5 #m in width and 26 nm thick, were patterned using electron beams whose lines had superconducting onsets above 90 K and zero resistance at 69 K after rapid thermal annealing. Both ion beam and laser patterning had similar superconducting onsets and zero resistance. Neodecanoates of Y, Yb, Ba, and Cu were formed, as previously described [5], by reacting the metal acetates of these materials with either ammonium neodecanoate or tetramethyl ammonium neodecanoate. The carboxylates formed from these reactions were then dissolved in a solution of xylene and pyridine. The individual chemical constituents were combined to produce solutions, Ln:Ba:Cu, in the ratio 1:2:4. Here, Ln is a rare-earth element. Details of the preparation of the metal carboxylates may be found elsewhere [6]. Thin films of Y-Ba-Cu and Yb-Ba-Cu were deposited onto <100> SrTiO by flooding the substrates with the appropriate neodecanoate solutions, then spin drying them at 2000 rpm for 30 s. The substrates were heated rapidly to 500°C for 5 min in an air oven to pyrolize the metallo organics to their oxides. This process produces thin films about 200 nm thick. The spin coating process was repeated 3-6 times if thicker films were desired. X-ray diffraction analysis of films pyrolized at 500°C shoed the presence of only microcrystallites. Room temperature resistivities of lx10 0-cm were measured for these films. No superconducting behavior was observed. After the 500°C pyrolysis the films were further processed by RTA in flowing oxygen. The substrates were placed upon oxidized silicon wafers, rapidly heated to 850°C for 60 s using infrared radiation produced by a bank of quartz lamps then allowed to cool to room temperature. A second rapid annealing was then performed at 920°C for 30 s in oxygen. Thin film superconductors formed in the manner described above were very uniform in structure and thickness across the surface of the film. The grains are approximately 1 #m wide and 2 #m long, a factor of 4 larger than the grains found in furnace annealed films formed by MOD [5].

The effect of the surface emissivity on lamp power and the measured pyrometer temperature is investigated by computer simulation. First, the effect of changing emissivity on wafer tempera-ture at constant lamp power (open loop control) during rapid thermal chemical vapor deposition (RTCVD) is demonstrated both experimentally as well. as simulated. Following this validation of the simulation, three control techniques are proposed which will maintain a constant wafer temperature during processing. These techniques still use a pyrometer or pyrometers as the temperature sensor(s). A control algorithm is developed for one of the techniques. The use of this algorithm is demonstrated via the computer simulation.

This paper describes studies of heat transfer in a rapid thermal processing-type oven used for several semiconductor wafer processes. These processes include 1) rapid thermal annealing, 2) thermal gradient zone melting, and 3) lateral epitaxial growth over oxide. The heat transfer studies include the measurement of convective heat transfer in a similar apparatus, and the development of a numerical model that incorporates radiative and convective heat transfer. Thermal stresses that are induced in silicon wafers are calculated and compared to the yield stress of silicon at the appropriate temperature and strain rate. Some methods of improving the temperature uniformity and reducing thermal stresses in the wafers are discussed.

The heat transfer to a wafer in a RTP furnace is simulated by an analytical/numerical model. The model includes radiant heat transfer to the wafer from the lamps, the heat conduction within the wafer, and the emission of radiation from the wafer. Geometric optics are used to predict the radiant heat flux distribution over the wafer. The predicted wafer surface temperature distribution is compared to measurements made in an RTP furnace for two different reflector geometries. Lamp configurations and the resulting heat flux that are required to produce a uniform wafer temperature are defined. Also investigated is the effect of patterns on the wafer surface temperature.

The effective emissivity of silicon varies with both temperature and the backside roughness of a wafer. Both of these variations need to be accounted for in the calibration of infrared optical pyrometers used in rapid thermal processing. A fully integrated hardware and software approach is described which calibrates the optical pyrometer over a temperature range of 350°C to 1275°C and provides for recalibration due to wafer to wafer variations in effective emissivity based on room temperature optical characterization of wafer backsides.

The emissivity of silicon wafers determine the temperature control in closed loop rapid thermal processing (RTP) systems. Silicon surface roughness, doping, and layers affect the intrinsic wafer emissivity, while RTP chamber walls reflectance reduces the amplitude of these effects. For temperatures below 600V, device side topography and layers also affect the emissivity of the wafer. Narrow band and wide band pyrometers show similar behavior with respect to layers on the wafer, as indicated by experimental and modeling techniques.

A method for evaluating temperature distributions between 400 °C and 600 °C have been studied by utilizing Si+ + B+ implantation. From the measurement of the sheet resistance(ps ), the equations shown in ps =3.8x10-8( t )-0.6 exp(Ea / kT) (Furnace anneal), Ps = 9.0x10-9( t )-0.5 exp( Ea / kT) (RTA) are obtained. And an obtained activation energy ( Ea) of 1.9eV is equivalent to that of solid phase epitaxial regrowth. From the distribution of the sheet resistance, the estimation of the temperature distribution between 400°C and 600 °C becomes possible for annealing times from lsec. to lhour.

During rapid thermal processing, temperature non-uniformities are created due to patterned layers on the wafers. A theoretical calculation of this non-uniformity is presented. Results are in good agreement with previously reported experimental results. The influence of the RTP-system design, concerning lamp-system, window-type and chamber reflectivity is studied. Also, the influence of pattern size and steady-state temperature is discussed. For the technological important case of Si02 patterns on Si, specific examples are calculated. As a conclusion it is shown that when the patterns are on the front-side, heating of the wafer should be restricted to the back-side of the wafer, while the front-side of the wafer should face a highly-reflecting chamber.

CVD is a well established deposition technology that is firmly embedded in the integrated processing line. Because CVD is a production worthy technology, there are advantages in using it to deposit state-of-the-art Si and Si heterostructural films. The requirements for such films are, among others, that they be thin (<100X), epitaxial with very low defect density, and that they be grown at low temperatures. These characteristics will ensure that there will be adequate carrier transport, resulting in fast devices, that the films will not significantly interdiffuse, and that metastable structures will be preserved.

Future integrated circuits manufacturing will require a new class of equipment where large size single wafers are processed and several fabrication steps can be performed sequentially in the same equipment. This is made possible by rapidly changing the wafer temperature and processing environment, and by employing in-situ cleaning and in-situ process monitoring. The implementation of multiple in-situ processing steps within the same equipment has the potential to reduce particulate contamination by improved control of the wafer environment and increase throughput by reducing overall processing time. This should prove to be invaluable for VLSI manufacturing. Furthermore, each isolated process module can be integrated or "clustered" to match processing needs in an "application specific" fashion. In this paper, a novel single wafer multiprocessing technology, rapid thermal processing chemical vapor deposition (RTP-CVD), is described and experimental results are presented for multilayer in-situ growth and deposition of semiconductors and dielectrics.

Rapid thermal chemical vapor deposition (RTCVD) of in-situ doped N and P-type thin single crystal silicon layers has been accomplished in a cold wall environment. Dichlorosilane, SiH2C12, is used for the silicon source, B2H6 and AsH3 for the dopant sources. Special attention is paid to minimize the oxygen and carbon contamination of the silicon surface prior to the deposition. As a result of process optimization, the total thermal budget of the RTCVD is reduced, junction abruptness is enhanced, dopant movement is minimized and the process-induced defects in the grown layer are remarkably reduced. The layers of single crystal silicon are examined by Fourier-transform infrared spectroscopy (FTIR), for thickness measurement and uniformity, modified Schimmel etch and Nomarski interference microscopy for defect delineation , secondary ion mass spectrometry (SIMS) and spreading resistance profile (SRP) for dopant profiling and junction depth measurements. Under optimized process conditions, single crystal silicon layers of high degree of structure quality with transition widths of 0.1 to 0.16 micron for three orders of magnitude change in dopant concentration are deposited. A systematic approach to optimize the process conditions for deposition of high quality and well-controlled single crystal silicon films is presented. It is demonstrated that the pre-growth process step(s) has a profound effect on the crystal quality of the grown layers. The process control features of RTCVD technology are addressed and the applications of thin, controllably-doped single crystal silicon layers for MOS and bipolar technologies are discussed.

The potential advantages of the rapid thermal processing (RTP) technique, in particular its accurate isothermal temperature and time control, motivated its use for alloying and sintering ohmic contacts to InP-based materials. Contact properties, such as stresses, were evaluated and compared to those of the same contacts fabricated by conventional heating cycles. The study included few different metal schemes, such as, Au-based alloys and several non-alloyed refractory systems as Ptai and W, which were deposited as ohmic contacts onto a variety of InP-based materials (InP, InGaAs, InGaAsP). The results revealed significant superiority of the non-alloyed contacts performance, both in the microstructure and electrical properties, demonstrating the potential of RTP as the standard heat treatment for ohmic contact fabrication to InP-based devices.

The reflectivity of thin film platinum silicide was measured, by means of a He - Ne laser, when samples of platinum films deposited on top of silicon wafers were annealed in a rapid thermal processor. This processor consists of two rows of tungsten - halogen quartz lamps placed above and below a quartz processing chamber. The thermal cycles consisted of a fast heating (about 200°C/s), followed by an isothermal plateau at temperatures ranging between 410 and 600°C. Films reflectivities dropped in two stages, due to the reaction between platinum and silicon. This two-stage drop was identified as due to the transformation of the platinum film, first into Pt2Si, and then into PtSi. The amounts of time required to complete the transformations were found to be in good agreement with the Arrhenius laws derived from the work of J.T. Pan and I.A. Blech on isothermal low-temperature (220 -330°C) sintering of platinum films on silicon, who unambigously established the correlation between reflectivity changes and silicide formation.

The Greater Silicon Valley Implant Users' Group (GSVIUG) has conducted several round robins to determine the uniformity and repeatability of modern rapid thermal processing (RTP) equipment. High-dose ion implants (5E15 As, 80keV) of 150mm wafers were used to monitor temperature distribution. Sheet resistance maps were then used to compare the uniformity and repeatability of each vendor's equipment. The results of the initial round robin evaluation showed that uniformity varied significantly with RTP vendor and implant conditions, ranging from 0.5% (one sigma/mean) to 14.0%. Vendors' RTP equipment shows a characteristics fingerprint on their sheet resistance maps, similar to the early maps of ion implant equipment. Maps from several round robins are presented that demonstrate problems with temperature distribution, chamber thermal memory, rapid edge cooling, and heat sink effects at wafer supports. Recent literature has focused on the importance of the RTP time-temperature profile. The short duration and high temperature of RTP make temperature and temperature distribution critical parameters that affect both the nature of the bulk defects as well as the final results of the implant-anneal process. This paper describes the material analysis of implanted wafers processed by various RTP equipment vendors. Results provided by spreading resistance probe (SRP) and secondary ion mass spectroscopy (SIMS) are compared with sheet resistance results. Conclusions about the time-temperature profile of RTP equipment will be made.

Deep-submicron MOSFET's require ultrathin (-.._ lOnm) gate dielectrics satisfying high performance and high reliability simultaneously. This paper proposes (reoxidized) nitrided oxides prepared by rapid isothermal processing (RIP) as a replacement of conventional gate-Si02 and investigates the physical properties, defect-charge densities, TDDB reliability, MOSFET performance, and hot-carrier reliability. In contrast with popularly heavy nitridations, light nitridation combined with the subsequent reoxidation improves reliability significantly, while achieving device performance comparable or superior to that of SiO2. An ultrathin (reoxidized) nitrided oxide prepared by RIP is most promising as the gate dielectric of deep-submicron MOSFET's in place of thermal SiO2.

In this paper, superior ultrathin oxynitride gate dielectrics have been fabricated using reactive rapid thermal processing, and their chemical, structural, and electrical properties have been studied and characterized. The techniques which are employed for oxynitride gate dielectrics formation include (i) in-situ multiple RTP of both thermal oxides and low-pressure chemical-vapor-deposited oxides in reactive gas ambient, and (ii) a novel in-situ multi-step deposition/growth rapid thermal processing chemical vapor deposition for oxide/nitride/oxide (ONO) stacked layer formation.

Yttrium oxide based metal-insulator-semiconductor (MIS) structures on silicon have been studied. Yttrium films were deposited by electron beam evaporation on Si and are then oxidized using an AG Associates Heat Pulse 410 rapid thermal processing (RTP) system. Two yttrium thicknesses (200 Å and 1000Å) were investigated. A second group of MIS structures were fabricated using electron beam deposited yttrium oxides which were subsequently annealed in the RTP system. Scanning electron microscopy shows that the thin yttrium oxide films have smooth surface morphology while the surface for thick oxide films is rough. The electrical properties of the rapidly oxidized yttrium films are compared with the rapidly annealed yttrium oxide films which exhibit superior dielectric properties. X-ray analysis is also conducted and has confirmed the formation of cubic yttrium oxide crystalline structures when the films are subjected to sufficient heat treatment.