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Design-Process-Technology Co-optimization for Manufacturability XII
Editor(s): Jason P. Cain
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Volume Details

Volume Number: 10588
Date Published: 23 May 2018

Table of Contents
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Front Matter: Volume 10588
Author(s): Proceedings of SPIE
Efficient place and route enablement of 5-tracks standard-cells through EUV compatible N5 ruleset
Author(s): L. Matti; V. Gerousis; M. Berekovic; P. Debacker; S. M. Y. Sherazi; D. Milojevic; R. Baert; J. Ryckaert; Ryoung-han Kim; Diederik Verkest; P. Raghavan
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Patterning method impact on sub-36nm pitch interconnect variability
Author(s): Nicholas V. LiCausi; James C.-H. Chen; R. S. Smith; E. Todd Ryan
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Applying machine learning to pattern analysis for automated in-design layout optimization
Author(s): Jason P. Cain; Moutaz Fakhry; Piyush Pathak; Jason Sweis; Frank Gennari; Ya-Chieh Lai
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Optimization of optical proximity correction to reduce mask write time using genetic algorithm
Author(s): Gregory J. Dick; Liang Cao; Abhishek Asthana; Jing Cheng; David N. Power
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Dependencies of bias tables to pattern density, critical dimension, global coordinates and pattern orientation for nanoimprint master manufacturing for the 200 mm wafer scale SmartNIL process
Author(s): P. Quemere; J. Chartoire; F. Delachat; F. Boudaa; L. Perraud; M. May; H. Teyssedre
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Pre-PDK block-level PPAC assessment of technology options for sub-7nm high-performance logic
Author(s): L. Liebmann; G. Northrop; M. Facchini; L. Riviere Cazaux; Z. Baum; N. Nakamoto; K. Sun; D. Chanemougame; G. Han; V. Gerousis
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Track height reduction for standard-cell in below 5nm node: how low can you go?
Author(s): S.M. Yasser Sherazi; Jung Kyu Chae; P. Debacker; L. Matti; P. Raghavan; V. Gerousis; D. Verkest; A. Mocuta; R.H. Kim; A. Spessot; J. Ryckaert
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A compact multi-bit flip-flop with smaller height implementation and metal-less intra-cell routing
Author(s): Jaewoo Seo; Jinwook Jung; Youngsoo Shin
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DTCO exploration for efficient standard cell power rails
Author(s): Bharani Chava; Julien Ryckaert; Luca Mattii; Syed Muhammad Yasser Sherazi; Peter Debacker; Alessio Spessot; Diederik Verkest
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Post-decomposition optimizations using pattern matching and rule-based clustering for multi-patterning technology
Author(s): Lynn T.-N. Wang; Sriram Madhavan
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Pin routability and pin access analysis on standard cells for layout optimization
Author(s): Jian Chen; Jun Wang; ChengYu Zhu; Wei Xu; Shuai Li; Eason Lin; Odie Ou; Ya-Chieh Lai; Shengrui Qu
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Variability-aware double-patterning layout optimization for analog circuits
Author(s): Yongfu Li; Valerio Perez; Vikas Tripathi; Zhao Chuan Lee; I-Lun Tseng; Jonathan Yoong Seang Ong
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Litho friendly via insertion with in-design auto-fix flow using machine learning
Author(s): Ahmed Mounir Elsemary; Moutaz Fakhry; Janam Bakshi; Nishant Shah; Mohamed Ismail; Fadi Batarseh; Uwe Paul Schroeder; Ahmed Mohyeldin; Jason Cain
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A model-based, Bayesian approach to the CF4/Ar etch of SiO2
Author(s): Meghali Chopra; Sofia Helpert; Rahul Verma; Zizhuo Zhang; Xilan Zhu; Roger Bonnecaze
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Hotspot detection based on surrounding optical feature
Author(s): Yayori Abe; Fumiharu Nakajima; Yuki Watanabe; Masanari Kajiwara; Shigeki Nojima; Toshiya Kotani
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Range pattern matching with layer operations and continuous refinements
Author(s): I-Lun Tseng; Zhao Chuan Lee; Yongfu Li; Valerio Perez; Vikas Tripathi; Jonathan Yoong Seang Ong
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Combinational optical rule check on hotspot detection
Author(s): Alexander Wei; Shaowen Gao; Yuansheng Ma; Shumay Shang; Yuyang Sun; Rui Wu; Lianghong Yin; Hongxin Zhang
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Pattern analysis and classification accelerates OPC tuning, monitoring, and optimization and mask inspection
Author(s): Ruoping Wang; Paul Lupa; Jason Sweis; Ya-Chieh Lai; Philippe Hurat
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IMEC N7, N5 and beyond: DTCO, STCO and EUV insertion strategy to maintain affordable scaling trend
Author(s): Ryoung-han Kim; Yasser Sherazi; Peter Debacker; Praveen Raghavan; Julien Ryckaert; Arindam Malik; Diederik Verkest; Jae Uk Lee; Werner Gillijns; Ling Ee Tan; Victor Blanco; Kurt Ronse; Greg McIntyre
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Relaxing LER requirement in EUV lithography
Author(s): Yandong Luo; Puneet Gupta
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Comparison between multi-colored LEn SADP/SAQP and selective-etching SADP/SAQP
Author(s): Ahmed Hamed Fatehy; Rehab Kotb; James Word
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Integrated manufacturing flow for selective-etching SADP/SAQP
Author(s): Rehab Kotb Ali; Ahmed Hamed Fatehy; James Word
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Timing optimization in SADP process through wire widening and double via insertion
Author(s): Youngsoo Song; Jinwook Jung; Daijoon Hyun; Youngsoo Shin
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Characterization of metal line-width variation in via first dual-damascene approach and its modeling using machine learning artificial neural network algorithms
Author(s): Pietro Cantù; Chiara Catarisano; Nicoletta Corneo; Alessandro Dundulachi; Emma Litterio; Valeria Mantovani; Matteo Patelmo; Benedetta Triulzi
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Cross-MEEF assisted SRAF print avoidance approach
Author(s): Vlad Liubich; William Brown; George Lippincott; Rui Wu
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A weak pattern random creation and scoring method for lithography process tuning
Author(s): Meili Zhang; Guogui Deng; Mudan Wang; Shirui Yu; Xinyi Hu; Chunshan Du; Qijian Wan; Zhengfang Liu; Gensheng Gao; Aliaa Kabeel; Kareem Madkour; Wael ElManhawy; Joe Kwan
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Pattern-based IP block detection, verification, and variability analysis
Author(s): Muhamad Asraf Bin Ahmad Ibrahim; Mohamad Fahmi Bin Muhsain; Ezni Aznida Binti Kamal Baharin; Jason Sweis; Ya-Chieh Lai; Philippe Hurat
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A smart way to identify and extract repeated patterns of a layout
Author(s): Fang Wei; Tingting Gu; Zhihao Chu; Chenming Zhang; Han Chen; Jun Zhu; Xinyi Hu; Chunshan Du; Qijian Wan; Zhengfang Liu
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Using pattern based layout comparison for a quick analysis of design changes
Author(s): Lucas Huang; Legender Yang; Huan Kan; Elain Zou; Qijian Wan; Chunshan Du; Xinyi Hu; Zhengfang Liu
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An efficient way of layout processing based on calibre DRC and pattern matching for defects inspection application
Author(s): Helen Li; Robben Lee; Tyzy Lee; Teddy Xue; Hermes Liu; Hall Wu; Qijian Wan; Chunshan Du; Xinyi Hu; Zhengfang Liu
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Leveraging pattern matching to solve SRAM verification challenges at advanced nodes
Author(s): Huan Kan; Lucas Huang; Legender Yang; Elaine Zou; Qijian Wan; Chunshan Du; Xinyi Hu; Zhengfang Liu; Yu Zhu; Recoo Zhang; Elven Huang; Jonathan Muirhead
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A portable pattern-based design technology co-optimization flow to reduce optical proximity correction run-time
Author(s): Yi-Chieh Chen; Tsung-Han Li; Hung-Yu Lin; Kao-Tun Chen; Chun-Sheng Wu; Ya-Chieh Lai; Philippe Hurat
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Hybrid hotspot library building based on optical and geometry analysis at early stage for new node development
Author(s): Ying Chen; Tianyang Gai; Xiaojing Su; Yayi Wei; Yajuan Su; Tianchun Ye
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