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PROCEEDINGS VOLUME 10148

Design-Process-Technology Co-optimization for Manufacturability XI
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Volume Details

Volume Number: 10148
Date Published: 17 May 2017
Softcover: 48 papers (442) pages
ISBN: 9781510607477

Table of Contents
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Front Matter: Volume 10148
Author(s): Proceedings of SPIE
Low track height standard-cells enable high-placement density and low-BEOL cost (Conference Presentation)
Author(s): Peter Debacker; Luca Matti; Syed M. Y. Sherazi; Rogier Baert; Vassilios Gerousis; Claire Nauts; Praveen Raghavan; Julien Ryckaert; Ryoung-Han Kim; Diederik Verkest
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Optimization of self-aligned double patterning (SADP)-compliant layout designs using pattern matching for sub-20nm metal routing
Author(s): Lynn T. - N. Wang; Uwe Paul Schroeder; Sriram Madhavan
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Pattern-based analytics to estimate and track yield risk of designs down to 7nm
Author(s): Jason P. Cain; Moutaz Fakhry; Piyush Pathak; Jason Sweis; Frank E. Gennari; Ya-Chieh Lai
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Redundant via insertion in self-aligned double patterning
Author(s): Youngsoo Song; Jinwook Jung; Youngsoo Shin
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Imbalance aware lithography hotspot detection: a deep learning approach
Author(s): Haoyu Yang; Luyang Luo; Jing Su; Chenxi Lin; Bei Yu
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Optimization of complex high-dimensional layout configurations for IC physical designs using graph search, data analytics, and machine learning
Author(s): Vito Dai; Edward Kah Ching Teoh; Ji Xu; Bharath Rangarajan
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Cost effective solution using inverse lithography OPC for DRAM random contact layer
Author(s): Jinhyuck Jun; Jaehee Hwang; Jaeseung Choi; Seyoung Oh; Chanha Park; Hyunjo Yang; Thuc Dam; Munhoe Do; Dong Chan Lee; Guangming Xiao; Jung-Hoe Choi; Kevin Lucas
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SOCS based post-layout optimization for multiple patterns with light interference prediction
Author(s): Taiki Kimura; Tetsuaki Matsunawa; Shigeki Nojima; David Z. Pan
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Design technology co-optimization (DTCO) study on self-aligned-via (SAV) with Lamella DSA for sub-7 nm technology
Author(s): Yuansheng Ma; Jongwook Kye; Gurdaman S. Khaira; Le Hong; James Word; Yuyang Sun; Joydeep Mitra; J. Andres Torres; Germain Fenger; Harry J. Levinson
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Efficient DSA-DP hybrid lithography conflict detection and guiding template assignment
Author(s): Jiaojiao Ou; Brian Cline; Greg Yeric; David Z. Pan
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Technology path-finding for directed self-assembly for via layers
Author(s): Yasmine Badr; Puneet Gupta
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Density driven placement of sub-DSA resolution assistant features (SDRAFs)
Author(s): Daifeng Guo; Maryann Tung; Ioannis Karageorgos; H.-S. Philip Wong; Martin D. F. Wong
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Exploiting regularity: breakthroughs in sub-7nm place-and-route
Author(s): L. Liebmann; V. Gerousis; Paul Gutwin; Xuelian Zhu; Jan Petykiewicz
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The effect of patterning options on embedded memory cells in logic technologies at iN10 and iN7
Author(s): Raf Appeltans; Pieter Weckx; Praveen Raghavan; Ryoung-Han Kim; Gouri Sankar Kar; Arnaud Furnémont; Liesbet Van der Perre; Wim Dehaene
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Design intent optimization at the beyond 7nm node: the intersection of DTCO and EUVL stochastic mitigation techniques
Author(s): Michael Crouse; Lars Liebmann; Vince Plachecki; Mohamed Salama; Yulu Chen; Nicole Saulnier; Derren Dunn; Itty Matthew; Stephen Hsu; Keith Gronlund; Francis Goodwin
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Identification and sensitivity analysis of a correlated ground rule system (design arc)
Author(s): Eric Eastman; Dureseti Chidambarrao; Werner Rausch; Rasit O. Topaloglu; Dongbing Shao; Ravikumar Ramachandran; Matthew Angyal
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Large marginal 2D self-aligned via patterning for sub-5nm technology
Author(s): Suhyeong Choi; Jae Uk Lee; Victor M. Blanco Carballo; Peter Debacker; Praveen Raghavan; Ryoung-Han Kim; Youngsoo Shin
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Routability enhancement through unidirectional standard cells with floating metal-2
Author(s): Jaewoo Seo; Youngsoo Shin
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Wafer hot spot identification through advanced photomask characterization techniques: part 2
Author(s): Yohan Choi; Michael Green; Young Cho; Young Ham; Howard Lin; Andy Lan; Richer Yang; Mike Lung
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Line-edge quality optimization of electron beam resist for high-throughput character projection exposure utilizing atomic force microscope analysis
Author(s): Rimon Ikeno; Yoshio Mita; Kunihiro Asada
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Quantifying electrical impacts on redundant wire insertion in 7nm unidirectional designs
Author(s): Ahmed Mohyeldin; Uwe Paul Schroeder; Ramya Srinivasan; Haritez Narisetty; Shobhit Malik; Sriram Madhavan
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Selection of airgap layers for circuit timing optimization
Author(s): Daijoon Hyun; Youngsoo Shin
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Systematic analysis of the timing and power impact of pure lines and cuts routing for multiple patterning
Author(s): Vinay Vashishtha; Lovish Masand; Ankita Dosi; Chandarasekaran Ramamurthy; Lawrence T. Clark
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Cutting-edge CMP modeling for front-end-of-line (FEOL) and full stack hotspot detection for advanced technologies
Author(s): Ushasree Katakamsetty; Jiansheng Jansen Chee; Yongfu Li; Chiu Wing Hui; Yaodong Huang; Ernesto Gene de la Garza
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Stitch overlap via coloring technique enables maskless via
Author(s): D. Civay; E. Laffosse
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Early stage hot spot analysis through standard cell base random pattern generation
Author(s): Joong-Won Jeon; Jaewan Song; Jeong-Lim Kim; Seongyul Park; Seung-Hune Yang; Sooryong Lee; Hokyu Kang; Kareem Madkour; Wael ElManhawy; SeungJo Lee; Joe Kwan
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Design space sampling using hierarchical clustering of patterns on a full chip
Author(s): Andrey Lutich
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A fuzzy pattern matching method based on graph kernel for lithography hotspot detection
Author(s): Izumi Nitta; Yuzi Kanazawa; Tsutomu Ishida; Koji Banno
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Design and pitch scaling for affordable node transition and EUV insertion scenario
Author(s): Ryoung-han Kim; Julien Ryckaert; Praveen Raghavan; Yasser Sherazi; Peter Debacker; Darko Trivkovic; Werner Gillijns; Ling Ee Tan; Youssef Drissi; Victor Blanco; Joost Bekaert; Ming Mao; Stephane Larivière; Greg McIntyre
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Transforming information from silicon testing and design characterization into numerical data sets for yield learning
Author(s): Thomas Yang; Yang Shen; Yifan Zhang; Jason Sweis; Ya-Chieh Lai
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A pattern-based design analysis method by using inline inspection data more efficiently
Author(s): Linda Zhuang; Annie Zhu; Yifan Zhang; Jason Sweis; Ya-Chieh Lai
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Low track height standard cell design in iN7 using scaling boosters
Author(s): S. M. Y. Sherazi; C. Jha; D. Rodopoulos; P. Debacker; B. Chava; L. Matti; M. G. Bardon; P. Schuddinck; P. Raghavan; V. Gerousis; A. Spessot; D. Verkest; A. Mocuta; R. H. Kim; J. Ryckaert
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Design space analysis of novel interconnect constructs for 22nm FDX technology
Author(s): Tuhin Guha Neogi; Navneet Jain; Piyush Verma; David Permana; Andrey Lutich; Francois Weishbuch; Deepal Wehella-Gamage; Benoit Francois Claude Ramadout; Gowtham Vangara; Juhan Kim; Thomas Herrmann; Kai Sun; Katherina Babich; David Pritchard; Mahbub Rashed
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IR-drop analysis for validating power grids and standard cell architectures in sub-10nm node designs
Author(s): Yongchan Ban; Chenchen Wang; Jia Zeng; Jongwook Kye
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A random generation approach to pattern library creation for full chip lithographic simulation
Author(s): Elain Zou; Sid Hong; Limei Liu; Lucas Huang; Legender Yang; Aliaa Kabeel; Kareem Madkour; Wael ElManhawy; Joe Kwan; Chunshan Du; Xinyi Hu; Qijian Wan; Recoo Zhang
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Gate tie-down construct in the 22FDX technology: a silicon-based method for layout optimization
Author(s): B. Ramadout; D. Wehella-Gamage; T. Staiger; H.-P. Moll; T.-Guha Neogi
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The new OPC method for obtaining the stability of MBAF OPC
Author(s): Jookyoung Song; Jaeseung Choi; Chanha Park; Hyunjo Yang; Daekwon Kang; Minsu Oh; Manjae Park; James Moon; Jun Ye; Stanislas Baron
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User-friendly design approach for analog layout design
Author(s): Yongfu Li; Zhao Chuan Lee; Vikas Tripathi; Valerio Perez; Yoong Seang Ong; Chiu Wing Hui
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A fast process development flow by applying design technology co-optimization
Author(s): Yi-Chieh Chen; Shin-Shing Yeh; Tsong-Hua Ou; Hung-Yu Lin; Yung-Ching Mai; Lawrence Lin; Jun-Cheng Lai; Ya Chieh Lai; Wei Xu; Philippe Hurat
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A novel approach of ensuring layout regularity correct by construction in advanced technologies
Author(s): Shafquat Jahan Ahmed; Yagnesh Vaderiya; Radhika Gupta; Chittoor Parthasarathy; Jean-Claude Marin; Frederic Robert
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Hotspots fixing flow in NTD process by using DTCO methodology at 10nm metal 1 layer
Author(s): Xiaojing Su; Lisong Dong; Jiaxin Lin; Ying Chen; Yayi Wei; Tianchun Ye; Chunshan Du; Feng Shao; Recco Zhang; Yu Zhu; Junjiang Lei; Minghui Fan
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Stitching-aware in-design DPT auto fixing for sub-20nm logic devices
Author(s): Soo-Han Choi; Sai Krishna K.V.V.S; David Pemberton-Smith
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Process weakness assessment by profiling all incoming design components
Author(s): Linda Zhuang; MengFeng Cai; Annie Zhu; Yifan Zhang; Jason Sweis; Ya-Chieh Lai
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Using pattern matching to increase performance in hotspot fixing flows
Author(s): Bradley J. Falch; Seung-Hee Baek; John Tsai; Mingchao Ji; Jun Zhu
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Litho hotspots fixing using model based algorithm
Author(s): Meili Zhang; Shirui Yu; Zhibiao Mao; Marwa Shafee; Kareem Madkour; Wael ElManhawy; Joe Kwan; Xinyi Hu; Qijian Wan; Chunshan Du
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Using design differentiating methods to find suspect design patterns which cause failure
Author(s): Yang Shen; Thomas Yang; Yifan Zhang; Jason Sweis; Ya-Chieh Lai
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Electrical failure debug using interlayer profiling method
Author(s): Thomas Yang; Yang Shen; Yifan Zhang; Jason Sweis; Ya-Chieh Lai
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A fast and efficient method for device level layout analysis
Author(s): YaoQi Dong; Elaine Zou; Jenny Pang; Lucas Huang; Legender Yang; Chunlei Zhang; Chunshan Du; Xinyi Hu; Qijian Wan
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Pattern database applications from design to manufacturing
Author(s): Linda Zhuang; Annie Zhu; Yifan Zhang; Jason Sweis; Ya-Chieh Lai
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Enhancing manufacturability of standard cells by using DTCO methodology
Author(s): Lijun Zhao; Ying Chen; Xiaojing Su; Yajuan Su; Yayi Wei; Tianchun Ye
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