This paper attempts to describe the advances of epitaxy of elemental and compound semiconductors and their impact on new physics, effects and applications of new devices. The impact of the recent epitaxy on material research is truly revolutionary. However, the scope is too immense to cover in a limited space and time. In lieu of the detailed descriptions of the epitaxial processes, I will try to highlight the most important substances of the advance. Several examples of newly discovered effects and new devices based on the artificially structured materials that are made possible by the advanced epitaxial techniques will be presented. These examples are by no mean exclusive and many other important ones are inadvertent omitted owing to the limited space and preferential interests of the author. Finally, some on-going research efforts as well as possible directions of further development of thin film epitaxy are discussed.

The formation of shallow junctions by rapid thermal annealing of BF2+ or B+ ion-implanted Si wafers was studied. Substantial differences in the dopant activation and junction depths were observed between the different samples for high-dose implantation. Dual implantation of B+ and F+ into Si was done so that the influence of flourine on dopant behavior could be studied. Flourine was found to have a marked effect and a model is proposed to account for the observations. Also, comparison between rapid thermal and conventional furnace annealing of the various implanted samples is discussed.

Device reliability is an important issue for the introduction of a new process technique. In this paper, our experimental findings regarding the performance and stability of devices fabricated by rapid thermal processing (RTP) are presented. Test structures for this study include p-n junction diode, metal-oxide-semiconductor (MOS) capacitor, and n-channel MOS field-effect-transistor (MOSFET). The integrity of p-n junction is found to be wellpreserved by RTP. Charge trapping in the gate oxide of MOS capacitor is highly dependent on the RTP temperature and can be reduced to the level of furnace processed capacitor at higher temperature RTP condition. The performance of fresh n-channel MOSFET fabricated by RTP can be superior to conventional furnace processed ones. However, higher substrate current and charge trapping in the gate oxide of RTP processed devices cause slightly higher device instability as compared to the furnace annealed devices after accelerated stress.

Pre-amorphisation of silicon substrates with a high dose of 28Si+ is known to suppress the axial channelling of subsequent low energy boron implants and thus lead to shallow junction formation. However, it is shown that for amorphous layer regrowth below 800°C a high concentration of deep level donor defects (1-2 x 1017 cm-3) remains in the tail of the Si + implant. These have been directly correlated with the large leakage current densities (up to 10-A/cm2) measured in these low temperature activated devices. Smaller (tilde 10-5 A/cm2) leakage current densities were found in similarly pre-amorphised n+p diodes. It is shown that the difference can be explained by the donors forming a floating, and less easily depleted, n-type region in the n+p diodes.

Silicon On Insulator technology is now reaching the point of actual application to a medium size circuit market. Three approaches have been extensively explored in order to obtain more or less defect-free SOI 4 in. wafers: zone melting recrystallization, formation and oxidation of porous-Si, and oxygen implantation. We review the advantages and drawbacks of these techniques and some electrical results obtained on circuits made on these SOI materials.

This paper presents a critical review of conventional and novel planarization processes such as Glass Flow, Etchback with or without a sacrificial layer, SOG, BSQ, Polyimide, Substrate-biased PECVD, and Pillars. Key issues in a planarization process, e.g., surface morphology, process simplicity and reliability, material characteristics, and etch control are discussed. A comparison of various planarization processes is tabulated. The future trend of the planarization technology is examined according to the above principles.

The formations of TiNx0y/TiSi2 bilayer on Si by rapid thermal nitridation of titanium silicide in NH3 as well as p+/n shallow junction using doped silicide technique have been studied. Results of the chemical stability of TiNx0v/TiSi7/Si in dilute HF, the effectiveness of TiNx0, on TiSi2 as a diffusion barrier Mr Al boron diffusion in Si02/TiSi,2/Si structure, the surface dopant concentration at the TiSi7/Si interface, and the junction quality are presented. It is found that TiNx0y/TiSi2 bilayer has good chemical stability in dilute HF for 60 sec and acts as an effeentive contact barrier between Al and Si substrate up to 500°C, 30 min. Shallow p±n junction with high boron concentration at the TiSO/Si interface has been formed. P-1-/n diodes and p-channel LDD MOSFETs fabricated using this technology show good I-V characteristics with a reverse leakage current on the order of 10-9A/cm.

We discuss the transient-enhanced diffusion of Sb, As, P, In, Ga, and B in ion-implanted Si, where the near-surface region has been amorphized by the dopant or by a self-implantation process. With Sb, a large transient diffusion enhancement is observed proportional to dopant concentration. For Sb, As, P, and In, the enhancement follows the relative interstitialcy diffusion coefficient. We believe this behavior is caused by stable implantation-induced point defects present in the amorphous surface layer, which decay during thermal processing to release high concentrations of self interstitials. This process occurs in competition with the solid phase epitaxial (SPE) growth process, and for high dopant concentrations can occur in the amorphous phase ahead of the crystallization front. We believe this may be the origin of the dopant redistribution which can occur during SPE growth, which sets the upper limit to the dopant concentration which can be incorporated in the lattice by SPE growth. These effects are reduced for Ga and are absent for B, although transient enhanced diffusion of these species can still occur from defects emitted from the damaged crystal underlying the original amorphous/crystalline interface.

High-temperature, oxygen ion implantation has been used to form buried oxide layers in silicon single crystals. The ion implantation and substrate variables, particularly the substrate temperature, were optimized to obtain silicon layers with appropriate microstructures near the surface. The as-implanted specimens were subsequently annealed at high temperatures to form buried Si02 layer with sharp interfaces and minimize dislocations in the top layers. These specimens were characterized by cross-section TEM and the results were compared with those obtained using spectroscopic ellipsometry (SE). We discuss the application of nondestructive SE technique in the characterization of silicon-on-insulator materials. Such techniques are absolutely essential for the fabrication of semiconductor devices.

Thin single crystalline layers of Ge with atomically sharp boundaries have been formed epitaxially on (100) Si substrates. This was done by 74Ge ion implantation into Si followed by steam oxidation. Using both Rutherford backscattering spectroscopy (RBS) and transmission electron microscopy (TEM), we have found that a Ge layer forms as a result of Ge segregated at the moving SiO2 interface during steam oxidation. For a SiO2 layer that has swept through the implanted region, essentially all of the Ge is snow-plowed and no Ge is lost to the oxide layer. The Ge layers and its two bounding interfaces, i.e., Ge/Si02 and Ge/Si, have been characterized as a function of the implantation dose and energy. The thickness of the Ge layer formed is dependent on the implantation dose. Thicknesses from a fraction of a monolayer to greater than 50 monolayers of Ge can be formed on Si by this mechanism. Initially the Ge layer forms a coherent interface with the underlying Si with no misfit dislocations, and misfit dislocations only appear as the thickness of the film is increased.

Photochemical effect on silicon surface cleaning and epitaxial film growth was investigated. Under ultraviolet light irradiation, the surface native oxide on the silicon substrate was removed at 730°C. An epitaxial film with high crystal quality was grown on the silicon substrate at a temperature as low as 540°C after thermal surface cleaning at980°C. The ultraviolet light irradiation seemed to be effective for gas-phase dissociation and surface reaction. Auto-doping was suppressed by using low temperature epitaxial growth and an almost ideal step junction was fabricated. A bipolar transistor having 65 nm epitaxially grown base layer was successfully operated.

Reactive plasma etching is being increasingly utilized in the fabrication of III-V - based electronic and optoelectronic devices. The high resolution and control afforded by dry etching processes have led to their rapid move from research to manufacturing applications. This paper will review some of those applications, processes, progress and problems associated with reactive plasma etching of III-V materials.

A phenomenological study of Reactive Ion Etching (RIE) of GaAs and Al.Gal_xAS (x=0.76) using BC13/CC12F2/He has been carried out in order to obtain equal rates for etching the two semiconductors with vertical walls and smooth etched surfaces. The influences of 02 and H2, added purposely or inadvertently, the roles of added CC1₂F₂ and He, and the effect of wafer size (loading effect) have been investigated on a limited basis. Equal etch rates, vertical (to tilde 1°) etched walls and smooth etched surfaces were attained for both GaAs and A1GaAs with and without a GaAs capping layer and with no special surface treatment of the wafers prior to etching in a commercially available RIE system used for the studies.

We present a low temperature (<300°C) plasma deposition process to prepare novel fluorine-containing silicon nitride films (p-SiN:F1 using SiH4-NF-N2 discharge mixtures at 14 MHz RF applied frequency. The deposition rate can be extremely high, up to 1600 A/min. p-SiN:F has electrical properties (dielectric constant, breakdown strength, resistivity, etc.) which compare favorably with high temperature CVD silicon nitride. By controlling the feed chemistry and physical variables of the discharge, a wide variety of film compositions are achieved. Two classes of films were identified as stable or unstable to air exposure and the instability of the films correlated with the atom fraction of fluorine initially incorporated. The results obtained from IR, AES, and RBS measurements show that low hydrogen-containing films are produced by the introduction of fluorine in the silicon nitride films. More importantly, the concentration of Si-H is extremely low because strong Si-F bonding replaces relatively weak Si-H bonds that satisfy free Si orbitals in conventional plasma nitride, and the hydrogen remaining in the film is present as stable N-H bonds. We believe this substitution of silicon-bound hydrogen, caused by the gas phase and surface-driven reactions, is a reason for superior film properties. The mechanism for this novel discharge chemistry is discussed.

Submicron silicon-nitride patterns were successfully formed by lift-off method using an electron cyclotron resonance (ECR)CVDsystem. In this system nitrogen or ammonia gas is introduced into the plasma chamber and is excited under ECR condition (2.45GHz microwave power and 875 Gauss magnetic flux density), and the plasma was extracted into deposition chamber filled with silane gas. The temperature of wafer surface increased gradually with increasing deposition time, but remained less than 105°C. A lift-off process with dimethyl ketone was carried out after slight-etching by hydro fluoric acid. Up to 5000Å thick patterns of SiN were formed. A 1500Å thick SiN pattern on GaAs wafer were annealed at 820°C for 20 minutes. SiN patterns maintained their shape and there was no out-diffusion of Ga and As into SiN. Films were characterized by FT-IR and ESR. Both SiN films formed by nitrogen and ammonia showed good etch resistance compared with films formed by plasma enhanced CVD or Sputtering.

Gallium Arsenide, unlike silicon does not have a natural oxide with the dielectric and interface qualities of SiO2. As a consequence alternative techniques have to be developed for device and IC processing applications. Plasma deposited silicon nitride films are currently being investigated in many laboratories. This paper will deal with the characterization of such films deposited under a range of gas and plasma deposition conditions. The techniques of Infra Red Spectroscopy and Rutherford backscattering have been used for characterization of both "as deposited layers" and layers which have been annealed up to temperatures of 800°C, after deposition. The use of RBS for silicon nitride on GaAs is limited since the relatively small nitride spectrum is superimposed on much larger GaAs spectrum. The problem can be removed by placing carbon test substrates alongside the GaAs wafers. This separates the silicon and nitrogen spectra from the substrate enabling enhanced accuracy to be obtained. In this paper the range of results obtained will be discussed in the context of the deposition condition in order to identify the optimum conditions for obtaining a stoichiometric compound and a high quality interface.

The chemical vapor deposition of metals induced by continuous laser irradiation of a substrate is modeled. The transient heat conduction problem is solved in the solid substrate, while the gas phase heat and mass transfer processes are assumed to be in a quasi-steady state. Temperature dependent parameters are used and irregularly shaped deposits are considered. Volcano-like deposition profiles are found to occur under certain conditions of gas pressure and laser intensity. The model predictions show that depletion effects and adsorption-desorption phenomena are major factors in the occurrence of volcano-like deposits.

Wet etching of (Al,Ga)As material and heterojunctions with etch speeds in the range of 3 to 4 Å/second using a citric acid based etch have been investigated by studying etch profiles and surface film formation. Etch mechanisms are identified based on observations of isotropic and preferential etching and surface film characteristics.

At this time there is evident a sharp increase of interest in the II-VI class of semiconducting compounds largely due to recent success in the growth of these materials by molecular beam epitaxy (MBE). One of the more important areas for application of high quality II-VI films is infrared imaging where CdTe deposited by MBE onto GaAs substrates is proposed as the substrate for subsequent HgCdTe and HgTe/CdTe superlattice deposition. Moreover, interest in the widegap II-VI compounds is stimulated by the need for electronically addressable flat panel display devices, and for the development of wide gap (blue) LED and injection laser devices. For applications in the blue portion of the visible spec-trum, ZnSe and ZnS have long been favored candidates. Very high quality ZnSe has recently been grown by MBE. The photoluminescence spectra of the MBE-grown ZnSe samples grown at Purdue and elsewhere strongly suggests that, in many cases, the film quality exceeds that obtainable in bulk form. In addition to the conventional II-VI materials, a new class of materials called diluted magnetic semiconductors (DMS) are currently receiving considerable attention. DMS are II-VI semiconductors such as CdTe or ZnSe with a fraction of the group II element substituted by a magnetic transition element such as Mn. The incorporation of Mn leads to very large magneto-optic effects, of the order of several hundred times that exhibited by conventional semiconductors of comparable bandgap. An especially significant feature of II-VI DMS materials is the increase in bandgap resulting from Mn incorporation. The bandgap increases with Mn mole fraction in a manner similar to the effect of Al in the (Ga,A1)As system, and with similar implications to the creation of quantum well structures and superlattices.

Unctoped Hga8Cd0,2Te alloys were annealed near the P-N conversion temperature region. Samples with various hole concentration were obtained. Optical absorption and Hall meas-urement were taken in the temperature range 77-300K. The measured wavelength ranged from the absorption edge to 30 dam. The temperature dependence of the absorption for low P-type alloys was observed. As the temperature decreases down from room temperature, the absorption decreases at first, and then increases. The intervalence cross section has been calculated with a band structure parameter P of 8x10 eV-cm and a heavy hole mass of 0.55m. Hole concentration for these alloys has been estimated by the absorption coefficient at 77K. The hole concentration as the function of annealing condition can be explained by the model of the mercury vacancy. The influence of the annealing condition on the sharpness of the absorption edge was observed. The absorption edge for high purity samples is steeper than those annealed at 350 degrees C.

The ability to convert a high quality single crystal superlattice structure into a high quality single crystal uniform alloy is a very important technological process. The phenomenon of impurity induced disordering (IID), by which the introduction of some impurity into the crystal lattice enhances the interdiffusion of the lattice constituent species, has been shown to be capable of achieving this homogenization of periodic structures. IID, first observed in 1980 by diffusion of zinc into AIGaAs superlattices, has received a great deal of attention in recent years. Many different impurities have proven capable of enhancing the rate of layer interdiffusion. Because of the complex interactions among the impurities and the atomic lattice, the magnitude of the increase in the lattice interdiffusion coefficient has been shown to depend strongly on the impurity species and the constituent compositions of the layers. Impurity induced disordering has been observed with impurities introduced in three different ways: diffusion from the surface, ion implantation, and doping during epitaxial growth. Selective disordering has been achieved by patterning this source, e.g., with a photolithographic mask or modulated-focused ion beam or by laser scanning. State-of-the-art index-guided lasers and lasers with non-absorbing facets have already been demonstrated using either Zn or Si as the impurity. It seems very likely that the process of impurity induced disordering will play a key role in the future of optoelectronic devices.

The disordering of All-xGaxAs/GaAs superlattices by ion-implantation has been studied by cross-sectional electron microscopy. It has been found that the superlattice intermixing is extensive only when accompanied by superlattice amorphization or impurity diffusion. Stacking-fault tetrahedra, interstitial dislocation loops and microtwins are the main types of defects observed after implantation and annealing. The defects are stratified and interact with the periodic strain-field of the superlattice.

Impurity and crystal defect induced compositional disordering of GaAs/AlxGai_xAs layered structures offers new microfabrication possibilities. By ion implantation one can control the location of the mixed region and control the degree of mixing. Specimens in this study were implanted with aluminum or silicon at energies and doses to give similar implanted-ion profiles. These were examined by cross-sectional transmission electron microscopy, secondary ion mass spectroscopy, and cathodoluminescence. The samples implanted with Al were found to partially disorder at a depth centered around the maximum damage peak. Silicon was found to disorder the material more completely than Al, and the disordered region extended to a depth greater than two times the projectile range. The effects of different annealing conditions on the disordering are discussed. We also implanted samples through high resolution ion masks and studied the disorder profile by TEM. The study revealed that the lateral disorder front follows that expected from the straggle of implanted ions. The feasibility of patterning with lateral resolution better than 30 nm is demonstrated. We have observed structure in spatially resolved cathodoluminescence, which we believe to arise from reduced dimensionality laterally patterned quantum wells.

Self-aligned-gate digital AlGaAs/GaAs MODFETs have been fabricated with gate lengths from 1.3 to 0.35 pm. A "T"cross-section gate formed by reactive ion etching (RIE) is employed. Rapid thermal annealing (RTA) is used for implant activation and ohmic contact alloying. High temperature stability of layer structures grown by molecular-beam epitaxy (MBE)and of refractory gate metallization is presented. Finally, a comparison of device characteristics is made for pulse-doped MODFETs with and without superlattice buffers, with emphasis on short channel effects.

Tungsten silicide has been successfully grown on GaAs using low pressure CVD. The growth mechanism is separated into surface-reaction-controlled and product-desorption-controlled regions. The former causes growth rate to increase with temperature, while the latter causes growth rate to decrease with temperature. High incorporation rate of silicon at the GaAs surface induces the Si/W ratio to go up with temperature at low temperature. The etching of Si by the product F- suppresses the growth rate at high temperature and high WF6 flow rate and also induces a critical dependence of Si/W ratio on WF6 flow rate. Tungsten silicide forms a hexagonal structure during deposition in the 370-450°C temperature range and changs to the tetragonal phase of WSi2 or W5Si3 depending on Si/W ratio after 800°C annealing. The interdiffusion of WSix/GaAs is serious at 800°C for high Si/W ratio (x>1), but no significant interdiffusion can be found for low Si/W ratio reflecting the fact that the Schottky barrier degrades to ohmic at 800°C for x=1 but still remains a good Schottky contact for x=0.6 and 0.4.

Profiles measured using secondary ion mass spectrometry for random and channeled implants of column II, IV, and VI elements in GaP, GaAs, InP, and InSb are decsribed. Depths and influence of furnace and lamp annealing on these profiles are emphasized.

A systematic investigation of high temperature stable metal contacts on GaAs using WSi2 as a diffusion barrier between the Ge and the Au metallization of a GaAs-Ge-WSi2-Au contact is presented. The effects of temperature stressing up to 610°C regarding the contact composition were characterized by XPS sputter profil-ing techniques and supported by electrical measurements of the contact parameters. It is shown that the con-tact system remains stable for long-term operation conditions at 350°C (e.g. 2oo hours). At much higher temperatures (610°C) interdiffusion between WSi2-Au and WSi2-Ge together with an additional diffusion of Ga into the metallization constitutes the lifetime limiting mechanism of such contacts.

Recent developments of optoelectronic integrated circuits (OEICs) will be discussed. Several key technologies required for OEICs, the present status of the technology and the application of OEICs are explained by introducing recent demonstrations of GaAs-based OEICs such as receivers and transmitters. Future development directed to higher productivity and utility of OEICs are also discussed.

Grating-surface-emitting diode lasers have the capability of producing a dynamically stable single-frequei cy output with angular beam divergences perpendicular to the grating lines of much less than 10. Because the emitting spot size of conventional edge emitting semiconductor lasers is very small, their beam divergences are very large: typically 70 parallel and 300 perpendicular to the p-n junction. In addition, the small optical spot size at the chip facet results in extremely high power densities (> 106 W/cm2) when driven to high power and ultimately causes catastrophic failure by melting the facet in AIGaAs lasers.

A technique for the reliable fabrication of gratings at 385nm periods in InP/InGaAsP has been demonstrated. A two stage RIE process involving an intermediate dielectric masking layer was used to produce grating with amplitudes up to 220nm. These structures have been successfully overgrown by LPE and processed into working DFB lasers.

Properties of GaAs and InGaAs/GaAs epitaxial interfaces formed by interrupted OMVPE regrowth are studied using C-V, I-V, DLTS, cross-sectional TEM and RBS techniques. Various types of anomalous depletion and accumulation carrier concentration profiles are observed at regrown interfaces prepared under various growth and processing conditions. Based on the detailed experiments, a new generalized model for regrown epitaxial interfaces is proposed and discussed which involves formation of gap state continuum as well as adsorption enhanced incorporation of shallow donor/acceptor impurity atoms. The introduction of gap state continuum is explained by the recently proposed disorder induced gap state (DIGS) model in which crystalline disorder within a few monolayers of the regrown interface region gives rise to state continuum, leading to the observed anomalous carrier profiles.

We report the use of chemically assisted ion beam etching (CAIBE) to form one mirror facet of GaAs/A1GaAs separate confinement single quantum well heterostructure lasers grown by metal-organic chemical vapor deposition (MOCVD). The other facet is formed by cleaving. Measurements of the light output from the etched, uncoated facets show that these devices are typically capable of a power output of 80 mW with a single-facet differential quantum efficiency of 32% pulsed (27% cw). This compares favorably with similar lasers which have both facets cleaved (40% pulsed and 40% cw). Threshold currents for the lasers (300 um long, 60 um stripe length) with one etched facet averaged 145 mA, and average catastrophic failure occurs at an average continuous power output of approximately 205 mW.

A hybridization technology for focal plane infrared detectors was developed. It is based on the user-friendly Beam-Lead hybridization technique which is particularly well suited for work with infrared detectors, such as HgCdTe, which are sensitive to mechanical action during processing. This technology permits high connection density for linear mosaic arrays with beam leads 6 µm length and 14 µm pitch. The beam lead's ability to be bonded to aluminum permits its interface with conventional silicon circuits.

Monte Carlo based microscopic techniques were used to study the stability and metastability of thin coherently strained layers of mismatched silicon-like semi-conductor material grown on the (111) silicon surface. The structural energy was calculated using three-body empirical potentials. For layers greater than roughly 20 A in thickness, the critical layer thickness associated with thermodynamic stability agrees quantitatively with continuum theory. For thinner layers, however, considerable variations from the continuum theory are found. For a strained layer six monolayers thick, the test system is found to be metastable against the nucleation of misfit dislocations to a lattice mismatch of approximately 11%, compared to the 4% equilibrium stability limit. Additionally, simulation of strained layer growth of two-dimensional Lennard-Jones crystal lattices has been performed using x.)lecular dynamics. In particular, we have studied the influences of lattice mismatch and substrate temperature on the growth, from the vapor phase, of overlayer material possessing a different bulk lattice constant than that of the substrate material. Simulation results predict that at substrate temperatures less than 50% of melting, epitaxial growth occurs for mismatch values less than 14% whereas above this value, defective growth is observed. At temperatures above 50% of the melt temperature, mass transport occurs across the layer interface and rapid diffusion is observed in the top-most atomic layers, resulting in liquid-like behavior in a thin layer over ordered strained layer crystal.

Specular CdTe films have been grown on (100), as well as 2°-6° off-oriented, Si substrates by low pressure metalorganic chemical vapor deposition method using dimethyl-cadmium (DMCd) and diethyl-telluride (DETe) as source materials. Growth temperatures range from 3450C to 4050C. 140K photoluminescence spectra show dominant sharp bound exciton related emission at 1.593 eV and weak defect related extrinsic band at 1.483 eV. The CdTe film grown at 375°C unity DMCd/DETe ratio has the lowest intensity ratio of I defect/I exciton. Sharp cubic phase structure with a preferential orientation of (111) is obtained for CdTe films grown at 355-375°C and for all 2°-6° off oriented (100) Si. Films grown at temperatures below 345°C and above 395°C exhibit x-ray diffraction patterns which contain extra hexagonal phase structures. Hall measurement and deep level transient spectroscopy are also used to characterize the electrical properties and defect levels of CdTe films. All grown CdTe are n-type with carrier concentration of about 1017cm-3 and mobilities of 500-600 cm2/V-sec at room temperature. Five levels, Ec-0.15, 0.25, 0.34, 0.57 and 0.76 eV, are observed in the near interface region of n-CdTe/P+-Si heterojunction.

It is well-known that the gate capacitance of MOS strut tures of n-channel inversion layers on small ptap semiconductors is a very important one since the MOS capacitance can be very easily controlled by varying the gate voltage and also since it explores various other fundamental aspects of semiconductor surfaces in MOS structures. However, the gate capacitance of MOS structures on ternary semiconductors has relatively been less investigated in the literature and an attempt is made for the first time to investigate theoretically the above capacitance on ternary compounds by using the three-band Kane model. We have derived an expression of the surface electron statistics without any approximations of low or high electric field limits and taking into account the influence of the Dingle temperature respectively. We have then formulated a model expression of the magneto gate capacitance with the proper use of the electron concentration. We shall also formulate the same capacitance for both the limits excluding he broadening of Landau levels for the purpose of comparison. It is observed, taking n-channel inversion layers on Hg1-x Cdx Te as an example that the gate capacitance exhibits spiky oscillations with " changinp, magnetic field and the oscillatory behaviour is in qualitative agreement with the experimental observation reported in the recent literature for MOS structure of Hg1-x Cdx Te. The corresponding results for n-channel inversion layers on relatively large band-gap semi-conductors both in the presence and absence of magnetic quantization can also obtained from the expressions derived.

GaAs self-aligned MESFETs with sub-micron gate were developed using buried p-layer(BP) to suppress short channel effects and applied to LSIs. According to calculation results, 200 to 300 mS/mm transconductance is necessary to realize 100 to 80 ps/gate propagation delay time in 1 k-gate LSIs. A half micron gate length SAINT FET exhibitrd transconductance in excess 200 mS/mm. BP-MESFETs were applied to ICs with operation clock cycles of 2 - Gb/s for about 250 gate scale and 700 Mb/s for 1 k-gate scale. Radiation hardness of 10 rad were tested. Technological advancements in barrier height enlargement related to amorphous silicon, three level interconnection, and rapid thermal annealing are described. In addition, the GaAs MESFET scaling law and estimated transconductance of 850 mS/mm is discussed.

Submicron channel MESFETs with a special electrode arrangement, previously described by Colquhoun and Ebert l have been fabricated and characterized. This overlapped gate configuration allows the channel length of the device to be substantially shorter than the gate metallization length. An extrinsic transconductance of more than 240 mS/mm, and a cutoff frequency fmax of 20 GHz have been obtained. Special care was taken to avoid parasitic current saturation effects in the ungated drain region by using a gate recess.

Various types of complementary HEMT logics thus far reported were compared from the point of view of the uniformity and the controllability of the threshold voltage of the FET. A selective crystal regrowth technique by MBE was developed for the complementary SISFET logic, which could grow a crystal with a smooth surface and did not affect the threshold voltage of the FET on the regrown crystal. A method how to control the flat-band voltage of GaAs SIS diode was reported, which preserve the feature of the uniformity of the flat-band voltage.

A high-transconductance AlGaAs/GaAs/AlGaAs selectively-doped double-heterojunction FET (SD-DH FET) with 1μm gate length has been fabricated by using high-quality epitaxial layer grown by MBE and Pd-buried gate structure. The double-heterojunction structure showed high sheet electron concentration of 2.5x10 12 /cm 2 and high electron mobility of 37000cm 2 /Vs at 77K. The sheet resistance at room temperature was 450 ohm/sq., which is about one half of that for a conventional high electron mobility transistor (HEMT). Systematic change of SD-DH FET characteristics with threshold voltage variation has been studied by gradually burying Pd into AlGaAs layer. It was found that transconductance of SD-DH FET monotonically increased for threshold voltage up to 0.1V, at which maximum extrinsic transconductance of 500mS/mm 7 was obtained. The estimated saturation velocity of electrons in SD-DH FET was 1.7 -2.0x10 7 cm/s, which is comparable to that of HEMT. The SD-DH FET has been shown to be superior to conventional HEMT fabricated at the same time in high current drivability, high transconductance and lower drain conductance.

The GaAs permeable base transistor (PBT) is fabricated by using overgrowth to embed a polycrystalline, submicrometer-period tungsten (W) grating completely within a single crystal of n-type GaAs. Recent PBTs have experimentally demonstrated an extrapolated maximum frequency of oscillation (f max)of 223 GHz and an extrapolated unity current gain frequency (fT) of 50 GHz. By using a subpicosecond laser sampling technique, the turn-on risetime for a PBT has been measured to be 5 picoseconds at room temperature. Initial PBT performance results were modest, prompting a comprehensive study of the special problems involved in fabrication. Extensive secondary ion mass spectrometry (SIMS) experiments have shown that Cr, Fe, Cu, Te, and Au impurities in the W grating lines diffuse into the GaAs during overgrowth. Similar experiments have shown that Cl preferentially incorporates from the gas phase around W gratings overgrown by AsCl, vapor phase epitaxy (VPE). Se shows this same behavior in organometallic chemical vapor deposition (OMCVD) overgrowth when H2Se is used as the dopant gas. Studies have also shown that any pre-overgrowth process-related surface contamination on the GaAs or the grating that is not removed by the pre-overgrowth surface cleaning will probably be incorporated into the overgrown GaAs. Many of these impurities are acceptors or deep levels in GaAs, and their presence in the device channels can have a strong negative effect on PBT performance. All of these fabrication-related problems have been rigorously addressed, and as a result both the device performance and the wafer-to-wafer reproducibility have improved substantially. The technology required to fabricate PBTs is not particularly difficult, provided that the proper combination of materials and processes is selected. Overgrowth-based technologies offer a whole new degree of freedom to high-speed device designers and those wishing to integrate disparate materials on a single wafer.

The resonant-tunneling Bipolar transistor (RBT) which has a high current gain of 20 was developed. RBTs are attracting a lot of interests as new functional and ultra high speed devices. We describe about material preparations and fabrication process technologies, and device characteristics.

A novel heterojunction FET employing a buried channel is presented. Insulated-gate FETs have been fabricated on MOCVD grown InP/In0.53 Ga0.47 As. Plasma-enhanced CVD was used for the gate insulator deposition. These devices showed transconductances up to 90 mS/mm, and improved drain-current stability as compared with InP MISFETs employing SiO2.

Two device structures are presented which could solve two problems that an AlGaAs heterojunction bipolar transistor faces when it is used in GaAs integrated circuits. The first is the 2kT surface recombination current problem which seriously reduces the current gain as the device area becomes sufficiently small. It is found that by sandwiching a high bandgap P-type AlGaAs in the emitter-base junction interface, the 2kT current could be substantially reduced and the current gain displays flattened characteristics at low collector current (<1 μA). The second problem is how to reliably smooth out the potential spike at the base-collector interface which results in a serious reach-through phenomenon in the common emitter I-V characteristics of the transistors. It is found that by adding a thin spacer layer with the same composition but the opposite type as the base layer in the base-collector junction interface, the potential spike can be easily and reproducibly suppressed.