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Proceedings Paper

A systematic approach for extracting verification patterns from an OPC test mask
Author(s): Mohammad K. A. Kamel; Mohamed Al-Imam
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Paper Abstract

Optical Proximity Correction (OPC) is a crucial step in Semiconductor manufacturing for technology of dimensions below the exposure wavelength. Light from the exposure source is diffracted when passing through mask dimensions below the exposure wavelength causing patterns on wafer to differ from the intent patterns. During OPC the design intent layout patterns are modified to compensate for light diffractions so that the final wafer patterns match the design intent patterns. OPC achieves this by using OPC models that model the optical conditions, resist, and etch behavior; and an OPC recipe that controls the patterns modification process. The OPC models are calibrated from test mask structures that are developed, exposed and measured when starting to set up the manufacturing process. Structures chosen to be placed on the test mask have a great impact on the capability to predict future layout patterns that were not present in the original test mask, referred to as model coverage. Test masks are usually composed of patterns used in model calibration and others used for verifying the calibrated model. In advanced technology nodes, both the feature size and the error budget are being shrunk. Hence to reach the best model coverage with acceptable accuracy, we need to ensure that the test mask contains all the possible structures in the real designs, while maintaining that the number of patterns does not consume long metrology tools time, cause extra overhead cost to the process, or delay the development cycle. This paper presents a systematic approach to optimize the number of patterns to be included in the test mask and split test patterns into calibration and verification patterns. Results from using the proposed method are compared to other methods of splitting that are based either on geometrical or random methods. The approach provided a significant reduction in model calibration time, the number of needed patterns in the test mask, and the total development process turn-around time; while maintaining the same accuracy that can be achieved from the original test patterns set.

Paper Details

Date Published: 29 June 2012
PDF: 8 pages
Proc. SPIE 8441, Photomask and Next-Generation Lithography Mask Technology XIX, 84410W (29 June 2012); doi: 10.1117/12.977202
Show Author Affiliations
Mohammad K. A. Kamel, Mentor Graphics Corp. (Egypt)
Mohamed Al-Imam, Mentor Graphics Corp. (Egypt)

Published in SPIE Proceedings Vol. 8441:
Photomask and Next-Generation Lithography Mask Technology XIX
Kokoro Kato, Editor(s)

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