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Proceedings Paper

Parallel Architecture For The Efficient Use Of Memory Subsystems In Image Processing
Author(s): Yu-Shan Fong; Abdullah Faruque
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Paper Abstract

Currently there exist many parallel computer architecture for image processing applications. The main goal of these architecture is to carry out image processing work in a highly parallel manner so that the processing time is short. In most of these architectures the processing elements are used very efficiently, but not the memory subsystems. Thus although the processing is done in parallel to ensure better response time, the available bandwidth is limited, in most cases, by the memory I/O operations. This paper introduces an MIMD (multiple instruction multiple data stream) type of parallel multimicroprocessor architecture for image processing. Our proposed architecture is one in which both the processors and the memory subsystems are kept as busy as possible in order to obtain faster response time and proper utilization of the hardware. The proposed architecture consists of an array of Processing Elements (PEs), a System Control Unit, and the main memory of the system. Each PE contains two Central Processing Unit (CPU), one is responsible for execution and the other is responsible for all memory operations. The overall response time of a task is faster because we divide the actual execution and the memory operation into two separate entities and carry them out concurrently. This is an improvement over the conventional architecture.

Paper Details

Date Published: 13 October 1987
PDF: 5 pages
Proc. SPIE 0845, Visual Communications and Image Processing II, (13 October 1987); doi: 10.1117/12.976527
Show Author Affiliations
Yu-Shan Fong, Clarkson University (United States)
Abdullah Faruque, Clarkson University (United States)


Published in SPIE Proceedings Vol. 0845:
Visual Communications and Image Processing II
T. Russell Hsing, Editor(s)

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