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Proceedings Paper

A VLSI Architecture For A Nonlinear Edge-Preserving Noise-Smoothing Image Filter
Author(s): Yannis Papananos; Dimitris Anastassiou
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Paper Abstract

A nonlinear, nonrecursive, two-dimensional filter has been developed for edge-preserving noise smoothing of images. It can also be beneficial as a pre-processor for data compression purposes. The filter is applied over a 3x3 window of pixels and uses an adaptive threshold. As with all image filters, the computational requirements lead to the utillization of special purpose VLSI hardware for real time implementation. The algorithm is being implemented in VLSI using a systolic array structure and parallel architecture, in which each processing element is assigned to one pixel. The structure of the processing element is very simple: except for some control gates and registers, it contains only a one-bit full adder as the main functional element. The most important feature of the proposed architecture is that the nonlinear operation has been implemented using no more than the simple tools and the silicon area required for a linear convolutional algorithm. Other properties of the above design are: simple interconnection scheme between processing elements and common control circuitry for all the processing elements on a single chip. Due to the topological simplicity of the processing element, arrays of size 16x16 cells per chip are believed to be feasible, using standard CMOS technology.

Paper Details

Date Published: 13 October 1987
PDF: 8 pages
Proc. SPIE 0845, Visual Communications and Image Processing II, (13 October 1987); doi: 10.1117/12.976521
Show Author Affiliations
Yannis Papananos, National Technical University of Athens (Greece)
Dimitris Anastassiou, Columbia University (United States)

Published in SPIE Proceedings Vol. 0845:
Visual Communications and Image Processing II
T. Russell Hsing, Editor(s)

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