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Proceedings Paper

A 13.5 Mhz Single Chip Multiformat Discrete Cosine Transform
Author(s): F. Jutand; N. Demassieux; M. Dana; J-P . Durandeau; G. Concordel; A. Artieri; E. Mackowiack; L. Bergher
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Paper Abstract

This communication presents a 2D Discrete Cosine Transform Processor realized with a single chip. Implementing a B.G Lee graph, it can perform DCT computation at the video rate of 13.5 MHz on blocks of a programmable size, from 16*16 to 4*4. Direct or inverse DCT computation is also programmable. The maximum computation error for a direct transform followed by an inverse transform is always better than 1 LSB. A hardwired, mapped architecture has led to a 39 mm2 silicon area for a 1.25μ CMOS 2-metal process.

Paper Details

Date Published: 13 October 1987
PDF: 7 pages
Proc. SPIE 0845, Visual Communications and Image Processing II, (13 October 1987); doi: 10.1117/12.976478
Show Author Affiliations
F. Jutand, ENST (France)
N. Demassieux, ENST (France)
M. Dana, ENST (France)
J-P . Durandeau, ENST (France)
G. Concordel, ENST (France)
A. Artieri, Thomson Semiconducteurs (France)
E. Mackowiack, Thomson Semiconducteurs (France)
L. Bergher, Thomson Semiconducteurs (France)


Published in SPIE Proceedings Vol. 0845:
Visual Communications and Image Processing II
T. Russell Hsing, Editor(s)

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