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Proceedings Paper

A Practical Real Time Svd Machine With Multi-Level Fault Tolerance
Author(s): David E. Schimmel; Franklin T. Luk
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Paper Abstract

A fault tolerant systolic processor system is proposed for computing the singular value decomposition of an nxn matrix. This approach uses only orthogonal interconnections and simple multiply and accumulate processors in the array. The fault tolerant properties are achieved through a composite of simple low overhead structures. The square root computations, and all fault tolerance computations are performed in one highly pipelined boundary processor. The architecture requires 0(n) processors and 0(n2 log n) time.

Paper Details

Date Published: 23 March 1986
PDF: 8 pages
Proc. SPIE 0698, Real-Time Signal Processing IX, (23 March 1986); doi: 10.1117/12.976256
Show Author Affiliations
David E. Schimmel, Cornell University (United States)
Franklin T. Luk, Cornell University (United States)


Published in SPIE Proceedings Vol. 0698:
Real-Time Signal Processing IX
William J. Miceli, Editor(s)

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