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Proceedings Paper

Signal Processing Applications Of 70 Mhz Bit-Serial Hardware
Author(s): Richard W. Linderman
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Paper Abstract

This paper examines signal processing applications of high speed bit-serial arithmetic and control circuitry which has been designed and tested for performance in the 50 MHz to 100 MHz range. A dense layout technique allows as many as 70 28-bit serial multipliers to be placed on a single 1.25 micron CMOS chip. At 70 MHz, this provides a throughput of 144 million multiplications per second. Applications to Fourier transform processors, digital filters, and matrix multi-plication are presented as examples. The bit-serial hardware is shown to have several advantages over bit-parallel alternatives.

Paper Details

Date Published: 23 March 1986
PDF: 6 pages
Proc. SPIE 0698, Real-Time Signal Processing IX, (23 March 1986); doi: 10.1117/12.976252
Show Author Affiliations
Richard W. Linderman, Air Force Institute of Technology (United States)


Published in SPIE Proceedings Vol. 0698:
Real-Time Signal Processing IX
William J. Miceli, Editor(s)

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