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Proceedings Paper

Architecture Of The Systolic Linear Algebra Parallel Processor (SLAPP)
Author(s): J. J. Symanski
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Paper Abstract

This paper will present preliminary concepts for the design of a systolic array of processors specifically aimed at efficient implementation of a core set of matrix operations consisting of matrix multiplication, QRD, SVD and generalized SVD. The algorithms to be implemented will be discussed briefly. Concepts for efficient implementation of the algorithms will be presented along with future plans.

Paper Details

Date Published: 23 March 1986
PDF: 5 pages
Proc. SPIE 0698, Real-Time Signal Processing IX, (23 March 1986); doi: 10.1117/12.976242
Show Author Affiliations
J. J. Symanski, Naval Ocean Systems Center (United States)


Published in SPIE Proceedings Vol. 0698:
Real-Time Signal Processing IX
William J. Miceli, Editor(s)

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