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Proceedings Paper

Fast Fourier Transform Co-processor (FFTC), towards embedded GFLOPs
Author(s): Christopher Kuehl; Uwe Liebstueckel; Isaac Tejerina; Michael Uemminghaus; Felix Witte; Michael Kolb; Martin Suess; Roland Weigand; Nicholas Kopp
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Paper Abstract

Many signal processing applications and algorithms perform their operations on the data in the transform domain to gain efficiency. The Fourier Transform Co-Processor has been developed with the aim to offload General Purpose Processors from performing these transformations and therefore to boast the overall performance of a processing module. The IP of the commercial PowerFFT processor has been selected and adapted to meet the constraints of the space environment. In frame of the ESA activity “Fast Fourier Transform DSP Co-processor (FFTC)” (ESTEC/Contract No. 15314/07/NL/LvH/ma) the objectives were the following: • Production of prototypes of a space qualified version of the commercial PowerFFT chip called FFTC based on the PowerFFT IP. • The development of a stand-alone FFTC Accelerator Board (FTAB) based on the FFTC including the Controller FPGA and SpaceWire Interfaces to verify the FFTC function and performance. The FFTC chip performs its calculations with floating point precision. Stand alone it is capable computing FFTs of up to 1K complex samples in length in only 10μsec. This corresponds to an equivalent processing performance of 4.7 GFlops. In this mode the maximum sustained data throughput reaches 6.4Gbit/s. When connected to up to 4 EDAC protected SDRAM memory banks the FFTC can perform long FFTs with up to 1M complex samples in length or multidimensional FFT-based processing tasks. A Controller FPGA on the FTAB takes care of the SDRAM addressing. The instructions commanded via the Controller FPGA are used to set up the data flow and generate the memory addresses. The paper will give an overview on the project, including the results of the validation of the FFTC ASIC prototypes.

Paper Details

Date Published: 8 November 2012
PDF: 9 pages
Proc. SPIE 8539, High-Performance Computing in Remote Sensing II, 853905 (8 November 2012); doi: 10.1117/12.974825
Show Author Affiliations
Christopher Kuehl, EADS Astrium (Germany)
Uwe Liebstueckel, EADS Astrium (Germany)
Isaac Tejerina, EADS Astrium (Germany)
Michael Uemminghaus, EADS Astrium (Germany)
Felix Witte, EADS Astrium (Germany)
Michael Kolb, Univ. of Applied Sciences (Germany)
Martin Suess, European Space Research and Technology Ctr. (Netherlands)
Roland Weigand, European Space Research and Technology Ctr. (Netherlands)
Nicholas Kopp, Hybrid DSP Systems (Netherlands)

Published in SPIE Proceedings Vol. 8539:
High-Performance Computing in Remote Sensing II
Bormin Huang; Antonio J. Plaza, Editor(s)

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