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Proceedings Paper

A Modular Ring Architecture for Large Scale Neural Network Implementations
Author(s): Lance B. Jump; Panos A. Ligomenides
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Paper Abstract

Constructing fully parallel, large scale, neural networks is complicated by the problems of providing for massive interconnectivity and of overcoming fan in/out limitations in area-efficient VLSI/WSI realizations. A modular, bus switched, neural ring architecture employing primitive ring (pRing) processors is proposed, which solves the fan in/out and connectivity problems by a dynamically reconfigurable communication ring that synchronously serves identical, radially connected, processing elements. It also allows cost versus performance trade-offs by the assignment of variable numbers of logical neurons to each physical processing element.

Paper Details

Date Published: 1 November 1989
PDF: 10 pages
Proc. SPIE 1199, Visual Communications and Image Processing IV, (1 November 1989); doi: 10.1117/12.970122
Show Author Affiliations
Lance B. Jump, University of Maryland (United States)
Panos A. Ligomenides, Caelum Research Corp. (United States)


Published in SPIE Proceedings Vol. 1199:
Visual Communications and Image Processing IV
William A. Pearlman, Editor(s)

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