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Proceedings Paper

Real-Time Focal-Plane Array Image Processor
Author(s): E-S. Eid; E. R. Fossum
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Paper Abstract

A focal-plane-array chip designed for real-time, general-purpose, image preprocessing is reported. A 48 X 48 pixel detector array and a 24 X 24 processing element processor array are monolithically integrated on the chip. The analog, charge-coupled device-based VLSI chip operates in the charge domain and has sensing, storing, and computing capabilities. It captures the image data and performs local neighborhood operations. The processor array is digitally programmable and uses a single-instruction, multiple-data parallel architecture. Various image preprocessing tasks such as level shifting, gain adjustment, thresholding, smoothing, sharpening, and edge detection can be implemented and A/D conversion can be performed prior to output. Frame-to-frame operations such as motion detection and tracking can be implemented as well. The chip was fabricated with a double-poly, double-metal process in a commercial CCD foundry. The prediction of the performance is based on numerical analysis and experimental results of testing a prototype charge-coupled computer. Operating at a modest clock frequency of 25 MHz, the chip is projected to achieve an internal throughput as high as 576 Mops with a 54 dB dynamic range (9-bit equivalent accuracy). The simulation of an edge detection algorithm implemented by the chip is presented. The power dissipation is estimated to be 20 mW and the total size of the 59-pad chip is 9.4 X 9.4 mm2.

Paper Details

Date Published: 1 February 1990
PDF: 11 pages
Proc. SPIE 1197, Automated Inspection and High-Speed Vision Architectures III, (1 February 1990); doi: 10.1117/12.969929
Show Author Affiliations
E-S. Eid, Columbia University (United States)
E. R. Fossum, Columbia University (United States)


Published in SPIE Proceedings Vol. 1197:
Automated Inspection and High-Speed Vision Architectures III
Michael J. W. Chen, Editor(s)

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