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Proceedings Paper

Bit-Serial Architecture For Real Time Motion Compensation
Author(s): Raffi Dianysian; Richard L. Baker
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Paper Abstract

We describe a bit-serial VLSI architecture for a real time motion estimation chip. The chip can search windows of arbitrary size with integer displacement resolution. Using 3 micron CMOS, it is projected to perform up to 6 million matches per second. This would permit real time exhaustive motion estimation of 8 x 8 blocks on 16 x 16 windows at NTSC resolution and 20 frames/sec. A short design time, without silicon assemblers or compilers, for the high speed chip is made possible by its bit-serial architecture.

Paper Details

Date Published: 25 October 1988
PDF: 8 pages
Proc. SPIE 1001, Visual Communications and Image Processing '88: Third in a Series, (25 October 1988); doi: 10.1117/12.969041
Show Author Affiliations
Raffi Dianysian, University of California Los Angeles (United States)
Richard L. Baker, University of California Los Angeles (United States)


Published in SPIE Proceedings Vol. 1001:
Visual Communications and Image Processing '88: Third in a Series
T. Russell Hsing, Editor(s)

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