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Proceedings Paper

VLSI Implementation Of Motion Compensation Full-Search Block-Matching Algorithm
Author(s): Kun-Min Yang; Lance Wu; Hyonil Chong; Ming-Ting Sun
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Paper Abstract

In this paper, we describe a single chip VLSI implementation of a Motion Compensation algorithm for a very low bit-rate motion video codec. Our design aims at implementing the Block Matching Algorithm (BMA). The novel features of our design are the followings: 1. It has full-search capability. 2. It allows sequential data inputs but performs parallel processing with 100% efficiency. 3. Common buses are used for data transfer. 4. It is a highly modular design and easy to expand. 5. It contains testing circuitry. The design has been laid out. Simulation results show that with the use of double metal 1.2µ CMOS process, the design will be able to run up to 25 MHz. The schematic design for fractional-precision block matching system is also described in this paper.

Paper Details

Date Published: 25 October 1988
PDF: 8 pages
Proc. SPIE 1001, Visual Communications and Image Processing '88: Third in a Series, (25 October 1988); doi: 10.1117/12.969040
Show Author Affiliations
Kun-Min Yang, Bellcore (United States)
Lance Wu, Bellcore (United States)
Hyonil Chong, Bellcore (United States)
Ming-Ting Sun, Bellcore (United States)


Published in SPIE Proceedings Vol. 1001:
Visual Communications and Image Processing '88: Third in a Series
T. Russell Hsing, Editor(s)

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