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Proceedings Paper

VLSI Architectures For Block Matching Algorithms
Author(s): P. Pirsch; T. Komarek
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Paper Abstract

This paper discusses architectures for realization of block matching algorithms with emphasis on highly concurrent systolic array processors. A three step mapping methodology for systolic arrays known from the literature is applied to block matching algorithms. Examples of 2-dimensional and 1-dimensional systolic arrays are presented. The needed array size, the transistor count and the maximum frame rate for processing video telephone and TV signals have been estimated.

Paper Details

Date Published: 25 October 1988
PDF: 10 pages
Proc. SPIE 1001, Visual Communications and Image Processing '88: Third in a Series, (25 October 1988); doi: 10.1117/12.969039
Show Author Affiliations
P. Pirsch, Institut fur Theoretische Nachrichtentechnik und Informationsverarbeitung (Germany)
T. Komarek, Institut fur Theoretische Nachrichtentechnik und Informationsverarbeitung (Germany)


Published in SPIE Proceedings Vol. 1001:
Visual Communications and Image Processing '88: Third in a Series
T. Russell Hsing, Editor(s)

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