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Proceedings Paper

VLSI Architectures For High Speed Two-Dimensional State-Space Recursive Filtering
Author(s): Jin Yun Zhang; Willem Steenaart
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Paper Abstract

This paper describes the problem of 2-D state-space filter algorithms and presents some high speed VLSI implementations. The state-space filters are known to be capable of minimizing the finite-word-length effects, but the computations will be increased. By exploiting concurrency in two-dimensional state-space systems, the following speed up architectures are obtained. The local speed-up processors realize the matrix-vector multiplications and decrease the processing time for each pixel. The global speed-up structures in addition use the inherent spatial concurrency and decrease the total processing time in a global sense. These architectures feature a high degree of parallelism and pipelining. They can work on multiple columns or multiple lines of images concurrently. The throughput rate can be up to one column or one line of images per clock time. Another high speed architecture, based on the 2-D block-state update technique, is then presented. It is shown that the throughput rate can be adjusted by varying the block size. Finally, comparisons among the different architectures are given in terms of hardware complexity, throughput rate, latency and efficiency.

Paper Details

Date Published: 25 October 1988
PDF: 8 pages
Proc. SPIE 1001, Visual Communications and Image Processing '88: Third in a Series, (25 October 1988); doi: 10.1117/12.968973
Show Author Affiliations
Jin Yun Zhang, University of Ottawa (Canada)
Willem Steenaart, University of Ottawa (Canada)


Published in SPIE Proceedings Vol. 1001:
Visual Communications and Image Processing '88: Third in a Series
T. Russell Hsing, Editor(s)

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