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Proceedings Paper

A Defect Reduction Methodology For Increased Sort Yield Using Automated Defect Inspection
Author(s): Christopher Radin
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Paper Abstract

This paper addresses the task of finding the source of defects that cause die failure at sort on semiconductor wafers. To do this, one must be able to determine defect type and density, in process, in order to determine where in the manufacturing process they are being created. Two methods have been commonly used. First is operator performed inspection of product or test wafers using a microscope. The second is short loop experiments using electrical test structures. Each of these methods have significant limitations when used for engineering analysis on VLSI technologies. Data generated by operator performed inspections show lack of reproducibility and large variations from operator to operator. Also, operator sensitivity declines to very low levels for defect sizes approaching linewidths in current semiconductor technologies. Electrical test structures require a conductive thin film to be patterned and etched. To get finer resolution of the section of the process causing a defect, indirect methods are required. This greatly constrains the options for experimental procedures. Because of the limitations on the methods described so far, defect reduction projects have been difficult, time consuming and prone to failure due to the difficulty of identifying the source of defects. Automated defect inspection, using the KLA-2020 automated wafer inspector, addresses these problems. This results in greatly increased efficiency and success rate. Presented in this paper is a discussion of the capabilities of automated defect inspection as compared to operator performed inspections and electrical test structure based short loop experiments. Also, a defect reduction methodology utilizing automated inspection will be described by presenting an actual example of its application. The methodology consists of using standard problem solving and experiment design techniques to isolate and solve major defect mechanisms. The example presented describes a series of short loop experiments using data generated by the KLA-2020 which successively narrowed down the portion of the process responsible. The problem was solved and a corresponding yield increase was seen.

Paper Details

Date Published: 1 January 1988
PDF: 10 pages
Proc. SPIE 0921, Integrated Circuit Metrology, Inspection, and Process Control II, (1 January 1988); doi: 10.1117/12.968369
Show Author Affiliations
Christopher Radin, Intel Corporation (United States)


Published in SPIE Proceedings Vol. 0921:
Integrated Circuit Metrology, Inspection, and Process Control II
Kevin M. Monahan, Editor(s)

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