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Proceedings Paper

Cel Resist Processing For Submicron CMOS And Bipolar Circuits
Author(s): K. E. Petrillo; M. J. Smyth; D. R. Hall
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Paper Abstract

A contrast enhancement layer (CEL) process was developed with a commercially available contrast enhancement material on top of a novalac-based resist for use on a 5X i-line stepper. This process extends the resolution capabilities to the 0.5μm range while maintaining vertical resist profiles at all measured dimensions up to 2μm. In comparison to an image reversal process capable of achieving submicron resolution, the CEL process technique has increased resolution, improved control of linewidth bias and exposure latitude, and has an exposure time of one half that of the image reversal process, increasing the throughput in the exposure tool. The CEL process was developed for both submicron CMOS and bipolar circuits. It was used at the emitter level of the bipolar process to pattern emitters of varying sizes down to 0.6μm by 4μm with the required vertical resist profile. The poly level of the submicron CMOS work was patterned using the CEL process with poly gates as small as 0.5μm. It has also been used at the contact hole level of the CMOS work, replacing a two layer resist system. An analysis of optical linewidth measurements from both the CMOS and bipolar circuits will be given.

Paper Details

Date Published: 1 January 1988
PDF: 9 pages
Proc. SPIE 0920, Advances in Resist Technology and Processing V, (1 January 1988); doi: 10.1117/12.968305
Show Author Affiliations
K. E. Petrillo, IBM (United States)
M. J. Smyth, IBM (United States)
D. R. Hall, IBM (United States)

Published in SPIE Proceedings Vol. 0920:
Advances in Resist Technology and Processing V
Scott A. MacDonald, Editor(s)

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