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Proceedings Paper

Optical Addressing Techniques For A Cmos Ram
Author(s): W. H. Wu; L. A. Bergman; R. A. Allen; A. R. Johnston
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Paper Abstract

Progress on optically addressing a CMOS RAM for a feasibility demonstration of free space optical interconnection is reported in this paper. The optical RAM chip has been fabricated and functional testing is in progress. Initial results seem promising. New design and SPICE simulation of optical gate cell (OGC) circuits have been carried out to correct the slow fall time of the 'weak pull-down' OGC, which has been characterized experimentally and reported previously. Methods of reducing the response times of the photodiodes and the associated circuits are discussed. Even with the current photodiode, it appears that an OGC can be designed with a performance that is compatible with a CMOS circuit such as the RAM.

Paper Details

Date Published: 1 January 1987
PDF: 8 pages
Proc. SPIE 0836, Optoelectronic Materials, Devices, Packaging, and Interconnects, (1 January 1987); doi: 10.1117/12.967551
Show Author Affiliations
W. H. Wu, California Institute of Technology (United States)
L. A. Bergman, California Institute of Technology (United States)
R. A. Allen, California Institute of Technology (United States)
A. R. Johnston, California Institute of Technology (United States)


Published in SPIE Proceedings Vol. 0836:
Optoelectronic Materials, Devices, Packaging, and Interconnects
Theodore E. Batchman; Richard Franklin Carson; Robert L. Galawa; Henry J. Wojtunik, Editor(s)

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