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Proceedings Paper

Residue-Based Image Processor For Very Large Scale Integration (VLSI) Implementation
Author(s): S. D. Fouse; G. R. Nudd; G. M. Thorne-Booth; P. A. Nygaard; F. D. Gichard
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Paper Abstract

This paper describes recent work undertaken at Hughes Research Laboratories, Malibu, California, in support of the DARPA Image Understanding (IU) program. The principal goal of the work is to investigate the application of VLSI technologies to IU systems and identify processor candidates well suited to VLSI implementation. One candidate that is very well suited to the VLSI technology is a programmable local-area processor with residue arithmetic based computations. The design and development of this processor, which operates on 5x5 kernel, are described. Of significant interest is an LSI custom circuit that we are developing and which will perform the bulk of the residue computations. In addition, an interface that will permit this processor to be controlled by a general-purpose host computer (e.g., PDP 11/34) is described.

Paper Details

Date Published: 12 November 1981
PDF: 11 pages
Proc. SPIE 0281, Techniques and Applications of Image Understanding, (12 November 1981); doi: 10.1117/12.965765
Show Author Affiliations
S. D. Fouse, Hughes Research Laboratories (United States)
G. R. Nudd, Hughes Research Laboratories (United States)
G. M. Thorne-Booth, Hughes Research Laboratories (United States)
P. A. Nygaard, Carlsbad Research Center (United States)
F. D. Gichard, Carlsbad Research Center (United States)


Published in SPIE Proceedings Vol. 0281:
Techniques and Applications of Image Understanding
James J. Pearson, Editor(s)

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