Share Email Print
cover

Proceedings Paper

General Purpose Very Large Scale Integration (VLSI) Chip For Computer Vision With Fault-Tolerant Hardware
Author(s): Michael R. Lowry; Allan Miller
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

This article describes a VLSI NMOS chip suitable for parallel implementation of computer vision algorithms. The chip contains a two dimensional array of processors, each connected to its four neighbors. Each processor currently has 32 bits of internal storage in three shift registers, and can do arbitrary boolean functions as well as serial bit arithmetic. Our objective is to make a vision processor with one processor for each pixel. This will require a very high density VLSI implementation, filling an entire wafer. We will need fault-tolerant hardware to deal with the fabrication errors present in such large circuits. We plan to do this by incorporating redundant links in the processor interconnections and routing the links around faulty processors. Current work focuses on testing a prototype chip with one processor, redesigning the chip for a more compact and regular layout, and designing the redundant link interconnections and hardware support for picture size arrays of processors.

Paper Details

Date Published: 12 November 1981
PDF: 4 pages
Proc. SPIE 0281, Techniques and Applications of Image Understanding, (12 November 1981); doi: 10.1117/12.965764
Show Author Affiliations
Michael R. Lowry, Stanford University (United States)
Allan Miller, Stanford University (United States)


Published in SPIE Proceedings Vol. 0281:
Techniques and Applications of Image Understanding
James J. Pearson, Editor(s)

© SPIE. Terms of Use
Back to Top