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Proceedings Paper

EUV and 193 mask line width roughness (LWR) impact on wafer CD LWR
Author(s): Chain Ting Huang; Cloud Cheng; Ming Jui Chen
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Paper Abstract

Influence of the mask error becomes serious because of the shrinkage of device pitch. The impact of mask line width roughness (LWR) on wafer CD needs to be studied on advanced node, because the device performance of semiconductor will be impacted seriously by wafer LWR/LER (line edge roughness). The Gate line width variation is a critical issue on advanced nodes. In this paper, we evaluate the LWR relationship between mask and wafer. We start the mask and wafer LWR study by simulation (aerial image model, and resist model) to see whether simulation meets optical theory. Besides, we also confirm the wafer printing result to compare simulation and wafer performance. Based on our study, simulation and wafer data show that the mask LWR has no obvious impact on wafer LWR even if on EUV (13.5nm wavelength) process.

Paper Details

Date Published: 29 June 2012
PDF: 9 pages
Proc. SPIE 8441, Photomask and Next-Generation Lithography Mask Technology XIX, 84410V (29 June 2012); doi: 10.1117/12.964397
Show Author Affiliations
Chain Ting Huang, United Microelectronics Corp. (Taiwan)
Cloud Cheng, United Microelectronics Corp. (Taiwan)
Ming Jui Chen, United Microelectronics Corp. (Taiwan)

Published in SPIE Proceedings Vol. 8441:
Photomask and Next-Generation Lithography Mask Technology XIX
Kokoro Kato, Editor(s)

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