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Proceedings Paper

An Integrated VLSI Design Environment
Author(s): Bruce W. Suter; Kevin D. Reilly
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Paper Abstract

On-going research on the development of an integrated VLSI design environment is presented. Although numerous VLSI design tools have been developed, previous approaches tend to attack the VLSI design environment in a fragmented fashion. This difficulty can be overcome by using an integrated simulation environment as the cornerstone upon which the VLSI design environment is built. Among the elements to be considered in an integrated VLSI design environment are multi-level functional/behavioral design specifications; simulators, optimizers, and design rule checkers; natural language user interface; and a knowledge base. In an environment context, new opportunities appear. For example, facilitation of the ability to generate revisions of VLSI devices in a relatively straight-forward manner over the lifecycle of a family of devices. Moreover, this endeavor can be viewed as a multi-level silicon compiler, which is embedded in a simulation environment.

Paper Details

Date Published: 26 March 1986
PDF: 6 pages
Proc. SPIE 0635, Applications of Artificial Intelligence III, (26 March 1986); doi: 10.1117/12.964174
Show Author Affiliations
Bruce W. Suter, University of Alabama at Birmingham (United States)
Kevin D. Reilly, University of Alabama at Birmingham (United States)


Published in SPIE Proceedings Vol. 0635:
Applications of Artificial Intelligence III
John F. Gilmore, Editor(s)

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