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Proceedings Paper

Optimization Of A Bilayer Resist Process For Polysilicon Gate Lithography
Author(s): Ludwik J. Zych; Gianpaolo Spadini; David A. Vidusek; Michael W. Legenza
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Paper Abstract

A high resolution, easy to implement bilayer PMGI [poly[dimethylglutarimiden process has been developed for producing polysilicon gates for high density CMOS. One micron wide, proximity effect free, and very uniform poly lines were obtained. Unbiased mask dimensions were reproduced easily with optimum process latitude. A focus latitude of 5 microns for 1 micron dense (repeating line/space) pattern is reported. This was achieved using a conventional stepper with a nominal resolution of 1.1 microns and a depth of focus of +/-1.3 microns. The delta between the mask and the final wafer dimensions was virtually the same for lines ranging from 5 all the way to 1 micron, as well as for all single and dense lines showing no proximity effects. The after-etch linewidths were uniform to within a sigma of 0.04 microns across a 4 inch wafer. The process consisted of the following: The polysilicon was coated with a planarizing and antireflecting PMGI layer of about 1 micron. A 0.7 micron layer of conventional novolak resist was put on top. The image was formed in the top resist and transferred to the bottom by a deep UV flood exposure. The PMGI was developed in a aqueous-based solution completely removing the top resist in the process. The etching was done in a single wafer RIE machine. All the linewidth measurements were made on final poly structures using electrical techniques. The advantages of using PMGI over conventional materials such as PMMA are no interlayer mixing, aqueous-based developer chemicals, and better etch resistance. The process is very flexible and different schemes can be implemented as needed. A novolak cap can be retained for increased etch resistance by changing to a different aqueous developer solution; however, the simple uncapped approach was found to be already far superior to any single layer resist technique and it was easily implemented on conventional production equipment.

Paper Details

Date Published: 9 July 1986
PDF: 7 pages
Proc. SPIE 0631, Advances in Resist Technology and Processing III, (9 July 1986); doi: 10.1117/12.963660
Show Author Affiliations
Ludwik J. Zych, VLSI Technology, Inc. (United States)
Gianpaolo Spadini, VLSI Technology, Inc. (United States)
David A. Vidusek, Shipley Company (United States)
Michael W. Legenza, Shipley Company (United States)


Published in SPIE Proceedings Vol. 0631:
Advances in Resist Technology and Processing III
C. Grant Willson, Editor(s)

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