Share Email Print

Proceedings Paper

Optical Clock Distribution To Silicon Chips
Author(s): B. D. Clymer; J. W. Goodman
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Timing constraints for state-of-the-art very large scale integrated circuits (VLSI) in silicon are rapidly approaching communication limits available with layered two-dimensional metal and polysilicon wiring approaches. For such communication-limited systems, reliable clock distribution is a key concern. The range of finite differences in signal delays over clock wires of various lengths for large chips creates a timing skew that is significant when compared to the switching time of transistors in the circuit. The high bandwidth and three-dimensionality of imaging optical systems suggest that optical clock distribution systems have the potential to overcome the timing barriers presented by planar wiring. Clock signals can be holographically mapped to detector sites within small functional cells on a chip surface. Within each functional cell, the clock is distributed via surface wires with negligible delays, reducing skew effects to the variation in reaction times of the photodetectors on the chip. Experiments simulating the response of optical clock detection circuits in standard 4 micron CMOS technology have been performed.

Paper Details

Date Published: 9 June 1986
PDF: 9 pages
Proc. SPIE 0625, Optical Computing, (9 June 1986); doi: 10.1117/12.963491
Show Author Affiliations
B. D. Clymer, Stanford University (United States)
J. W. Goodman, Stanford University (United States)

Published in SPIE Proceedings Vol. 0625:
Optical Computing
John A. Neff, Editor(s)

© SPIE. Terms of Use
Back to Top