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Proceedings Paper

Laser Testing of Integrated Circuits (ELASTIC®)
Author(s): Robert H. Jones
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Paper Abstract

The inadequacy of the stuck-at fault model has been well aired and documented.1 ,2 All studies agree that this model does not reflect the physical failures of real devices,3 principally because such failures do not exhibit a 1:1 mapping onto the logic domain.2 ,4 Circuit layouts which are based on stick diagrams do however reflect the physical domain in sufficient detail (see Fig. 1) to enable both structural defects, together with shorts and opens in metallic and non-metallic domains, to be detected and located. The author has proposed the adoption of a novel method which processes information obtained from a scanning laser beam reflected from a surface profile. Scanning may be of a raster nature over the surface, or follow a suitable path search along metal lines. The latter search type has been simulated in PROLOG. Such a topological approach to the testing problem offers a test structure for exploitation using a laser beam probe technique. In this paper the theory of reflectivity is described as it relates to the test method, and the results presented are based upon reflectance measurements obtained by raster scanning.

Paper Details

Date Published: 23 January 1990
PDF: 13 pages
Proc. SPIE 1180, Tests, Measurements, and Characterization of Electro-Optic Devices and Systems, (23 January 1990); doi: 10.1117/12.963455
Show Author Affiliations
Robert H. Jones, ILEA (United Kingdom)


Published in SPIE Proceedings Vol. 1180:
Tests, Measurements, and Characterization of Electro-Optic Devices and Systems
Shekhar G. Wadekar, Editor(s)

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