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Proceedings Paper

Optimizing Architectures For Parallel FFT Processing
Author(s): R. Keith Bardin; J. Daryl Sisk
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Paper Abstract

In the design of high-performance embedded processor systems dedicated to a predefined range of tasks, the best designs will result from the simultaneous optimization of the hardware architecture and the algorithms for the required task suite. This paper presents studies in progress of techniques for such optimizations applied to synthetic-aperture radar (S AR) and inverse SAR (ISAR) image processing algorithms. Our approach has been to implement scaled-down model calculations of real test problems on a variable-topology parallel test processor. We present here some initial results on the parallelization of the fast Fourier transform (.1-F1) algorithm from this investigation, and propose an enhancement of the hypercube processor topology which appears advantageous for many applications.

Paper Details

Date Published: 6 December 1989
PDF: 10 pages
Proc. SPIE 1154, Real-Time Signal Processing XII, (6 December 1989); doi: 10.1117/12.962380
Show Author Affiliations
R. Keith Bardin, Lockheed Palo Alto Research Laboratories (United States)
J. Daryl Sisk, Lockheed Palo Alto Research Laboratories (United States)


Published in SPIE Proceedings Vol. 1154:
Real-Time Signal Processing XII
J. P. Letellier, Editor(s)

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