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Proceedings Paper

Implementing A 64kbit/s Video Codec On DSP Hardware
Author(s): Luis de Sa; Victor Silva
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Paper Abstract

A modular hardware architecture for video coding at p x 64kbit/s data rates is described. The codec uses several digital signal processors (DSPs) and can be viewed as a single instruction multiple data (SIMD) computing architecture. Every image in a sequence is divided in regions of horizontal strips and each region is operated by its an processor. These local processors communicate with a central processor which codes (decodes) the cosine transformed frame differences. Lateral communication between adjacent processors is also permitted. This is done by memory sharing and allows comparisons between blocks situated in neighbouring regions, as required by most motion estimation algorithms. The codec is built using the modern TMS320C30 digital signal processor. The number of processors used in both the coder and the decoder depends on the application. This is a consequence of the modular design and allays the machine to be configured to suit a particular algorithm complexity or a desired quality of the coded image.

Paper Details

Date Published: 30 January 1990
PDF: 8 pages
Proc. SPIE 1153, Applications of Digital Image Processing XII, (30 January 1990); doi: 10.1117/12.962312
Show Author Affiliations
Luis de Sa, University of Coimbra (Portugal)
Victor Silva, University of Coimbra (Portugal)


Published in SPIE Proceedings Vol. 1153:
Applications of Digital Image Processing XII
Andrew G. Tescher, Editor(s)

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