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Proceedings Paper

Silicon-Implanted Thermally-Annealed N-InP Layers For Microwave Power MISFETs
Author(s): S. G. Liu; P. D. Gardner; S. Y. Narayan; J. B. Klatskin; S. D. Colvin
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Paper Abstract

This paper presents the electrical characteristics of InP layers produced in semi-insulating (SI) InP by Si implantation and thermal annealing. We also describe the performance of microwave power MISFETs fabricated on implanted/annealed N+N layers. The implanted layers were activated using an operationally-simple proximity anneal technique. The all-implanted power MISFETs were fabricated using a low (<1011 cm-2 eV-1) interface-density gate-oxide (Si02) layer that results in long-term drain current drift of less than 5%. Power output of 250 mW with 6-dB gain and 26% power-added efficiency was obtained at 10 GHz from 1-µm-gatelength MISFETs having 560-μm periphery. Cutoff frequencies of 43 GHz were deduced from S-parameter data measured on these devices.

Paper Details

Date Published: 28 November 1989
PDF: 9 pages
Proc. SPIE 1144, 1st Intl Conf on Indium Phosphide and Related Materials for Advanced Electronic and Optical Devices, (28 November 1989); doi: 10.1117/12.962046
Show Author Affiliations
S. G. Liu, David Sarnoff Research Center (United States)
P. D. Gardner, David Sarnoff Research Center (United States)
S. Y. Narayan, David Sarnoff Research Center (United States)
J. B. Klatskin, David Sarnoff Research Center (United States)
S. D. Colvin, David Sarnoff Research Center (United States)


Published in SPIE Proceedings Vol. 1144:
1st Intl Conf on Indium Phosphide and Related Materials for Advanced Electronic and Optical Devices

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