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Proceedings Paper

A New Fabrication Approach For Planar, Ion-Implanted InP JFETs
Author(s): J. B. Boos; W. Kruppa; B. Molnar
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Paper Abstract

A new, planar, fully ion-implanted indium phosphide (InP) junction field-effect transistor (JFET) fabrication process is described which utilizes n* source-drain implantation, Be and Be/P p+ gate implantation, a AuZn/Ni/TiW/Au gate metallization and proximity rapid thermal annealing. The JFETs exhibit a gate leakage current of approximately 40 nA at -8 V for a 1 pm x 150 μm gate, a reverse breakdown voltage of 17.5 V at 25 μA, and a maximum transconductance of 140 mS/mm. The addition of a Ni layer in the gate metallization significantly improves its adhesion. The specific contact resistance of the new gate structure is measured to be as low as 2 x 105 ohm-cm2,which is the lowest value reported to date for contacts to p-type InP.

Paper Details

Date Published: 28 November 1989
PDF: 6 pages
Proc. SPIE 1144, 1st Intl Conf on Indium Phosphide and Related Materials for Advanced Electronic and Optical Devices, (28 November 1989); doi: 10.1117/12.962015
Show Author Affiliations
J. B. Boos, Naval Research Laboratory (United States)
W. Kruppa, Naval Research Laboratory (United States)
B. Molnar, Naval Research Laboratory (United States)


Published in SPIE Proceedings Vol. 1144:
1st Intl Conf on Indium Phosphide and Related Materials for Advanced Electronic and Optical Devices

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