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Proceedings Paper

Fault Tolerance Techniques For Highly Parallel Signal Processing Architectures
Author(s): Jacob A. Abraham
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Paper Abstract

This overview paper describes techniques for fault tolerance which can be applied to highly parallel signal processing architec-tures. Classical techniques are outlined and shown applicable to memories and data communications. The recent approach of algorithm-based fault tolerance, which tailors the fault tolerance to the systolic algorithm and processor architecture, is shown to be a natural one for such systems. Various data encoding techniques and resulting fault-tolerant systems are described and critiqued.

Paper Details

Date Published: 28 July 1986
PDF: 17 pages
Proc. SPIE 0614, Highly Parallel Signal Processing and Architectures, (28 July 1986); doi: 10.1117/12.960498
Show Author Affiliations
Jacob A. Abraham, University of Illinois (United States)

Published in SPIE Proceedings Vol. 0614:
Highly Parallel Signal Processing and Architectures
Keith Bromley, Editor(s)

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