Proceedings Paper'Intelligent Memory Chips' Give Fully Programmable Synaptic Weights
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A fundamental stumbling block - defining a new set of extremely powerful and flexible building blocks with which to build neurocomputers - has recently been removed by Oxford Computer. The result is a family of digital, memory-plus-processor chips, or "Intelligent Memory Chips". These chips combine a high-capacity memory with massively parallel, slice-type processor logic. Unlike common memory chips that only store information, Intelligent Memory Chips perform intensive computations upon matrices they store. As a result, neural networks with fully programmable, signed synaptic weights can be built. The weights are modified as easily, precisely and stably as writing data into ordinary memory chips. Many forms of matrix-vector multipliers, 1- and 2-dimensional convolvers, and Fast Fourier and other transformers can be built as well to implement classical digital signal processing, pattern recognition, adaptive control and 3-dimensional graphics structures. Multiple Intelligent Memory Chips work together to provide the precision, matrix size and performance desired. Extremely large numbers of densely interconnected, artificial neurons in many layers can be provided. Networks easily interface to existing, non-neural machines. Network performance ranging from tens-of-billions to tens-of-trillions of operations per second may be built using current to near term semiconductor technology. Initial chips are being built using 1-micron, silicon CMOS and static RAM technology. The impacts of alternative memory technologies, and improvements in memory and fabrication technology are also discussed.