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Proceedings Paper

A 2-D Convolver Architecture For Real-Time Image Processing
Author(s): David Landeta; Chris W. Malinowski
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Paper Abstract

This paper presents a novel architecture for two VLSI ICs, an 8-bit and 12-bit version, which execute real-time 3x3 kernel image convolutions at rates exceeding 10 ms per 512x512 pixel frame (at a 30 MHz external clock rate). The ICs are capable of performing "on-the-fly" convolutions of images without any need for external input image buffers. Both symmetric and asymmetric coefficient kernels are supported, with coefficient precision up to 12 bits. Nine on-chip multiplier-accumulators maintain double-precision accuracy for maximum precision of the results and minimum roundoff noise. In addition, an on-chip ALU can be switched into the pixel datapath to perform simultaneous pixel-point operations on the incoming data. Thus, operations such as thresholding, inversion, shifts, and double frame arithmetic can be performed on the pixels with no extra speed penalty. Flexible internal datapaths of the processors provide easy means for cascadability of several devices if larger image arrays need to be processed. Moreover, larger convolution kernels, such as 6x6, can easily be supported with no speed penalty by employing two or more convolvers. On-chip delay buffers can be programmed to any desired raster line width up to 1024 pixels. The delay buffers may also be bypassed when direct "Sum-Of-Products" operation of the multipliers is required; such as when external frame buffer address sequencing is desired. These features make the convolvers suitable for applications such as affine and bilinear interpolation, one-dimensional convolution (FIR filtration), and matrix operations. Several examples of applications illustrating stand-alone and cascade mode operation of the ICs will be discussed.

Paper Details

Date Published: 30 August 1989
PDF: 11 pages
Proc. SPIE 1098, Aerospace Pattern Recognition, (30 August 1989); doi: 10.1117/12.960445
Show Author Affiliations
David Landeta, Harris Semiconductor (United States)
Chris W. Malinowski, Harris Semiconductor (United States)


Published in SPIE Proceedings Vol. 1098:
Aerospace Pattern Recognition
Marshall R. Weathersby, Editor(s)

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