Share Email Print
cover

Proceedings Paper

Recent Advances In Z-Technology Architecture
Author(s): David Ludwig; Daryl Smetana; Stuart Shanken
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Z-technology utilizes the process of stacking integrated circuits (ICs) to achieve a high degree of packaging density. This technique has been most commonly applied to packaging read out electronics for infrared (IR) focal plane arrays to achieve more signal processing at the detector interface. Irvine Sensor Corporation's (ISC's) standard packaging technology, called HYMOSS (HYbrid Mosaic On Stacked Silicon), has been tailored for stacking 0.004- inch thick silicon integrated circuits of custom designed read out electronics. New advances have been made which allow for stacking; non-silicon ICs, commercial (non-custom) circuits, and/or ICs which have been thinned to 0.002 inches.

Paper Details

Date Published: 13 September 1989
PDF: 11 pages
Proc. SPIE 1097, Materials, Devices, Techniques, and Applications for Z-Plane Focal Plane Array, (13 September 1989); doi: 10.1117/12.960376
Show Author Affiliations
David Ludwig, Irvine Sensors Corporation (United States)
Daryl Smetana, Irvine Sensors Corporation (United States)
Stuart Shanken, Irvine Sensors Corporation (United States)


Published in SPIE Proceedings Vol. 1097:
Materials, Devices, Techniques, and Applications for Z-Plane Focal Plane Array
John C. Carson, Editor(s)

© SPIE. Terms of Use
Back to Top