Share Email Print
cover

Proceedings Paper

Novel CCD Image Processor For Z-Plane Architecture
Author(s): S. E. Kemeny; E.S. Eid; E. R. Fossum
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

The use of charge-coupled device (CCD) circuits in Z-plane architectures for focal-plane image processing is discussed. The low-power, compact layout nature of CCDs makes them attractive for Z-plane application. Three application areas are addressed; non-uniformity compensation using CCD MDAC circuits, neighborhood image processing functions implemented with CCD circuits, and the use of CCDs for buffering multiple image frames. Such buffering enables spatial-temporal image transformation for lossless compression.

Paper Details

Date Published: 13 September 1989
PDF: 7 pages
Proc. SPIE 1097, Materials, Devices, Techniques, and Applications for Z-Plane Focal Plane Array, (13 September 1989); doi: 10.1117/12.960372
Show Author Affiliations
S. E. Kemeny, Center for Telecommunications Research (United States)
E.S. Eid, Center for Telecommunications Research (United States)
E. R. Fossum, Center for Telecommunications Research (United States)


Published in SPIE Proceedings Vol. 1097:
Materials, Devices, Techniques, and Applications for Z-Plane Focal Plane Array
John C. Carson, Editor(s)

© SPIE. Terms of Use
Back to Top