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Proceedings Paper

Microprocessor Arrays For Parallel Pattern Recognition
Author(s): Harvey R. Seliner
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Paper Abstract

The pricing structure of the new "third generation" microprocessors has made multiprocessing economically attractive. Nevertheless, changes are necessary in the classical Von Neuman hierarchy of computer elements in order to implement a parallel CPU (central processing unit) concept. Therefore, an innovative technique is explored in this report that utilizes truly parallel processors in handling arrays of data. The technique uses processors which perform identical operations on different data to multiply computing speed. In this configuration, there is no theoretical upper limit to the number of processors used. An application of an array processor to pictorial pattern recognition is examined. In this example, 108 inexpensive microprocessors are utilized in an array to obtain an equivalent computing speed of 420 MIPS (million instructions per second). The hardware configuration, timing considerations, and software requirements are also presented.

Paper Details

Date Published: 8 December 1977
PDF: 10 pages
Proc. SPIE 0119, Applications of Digital Image Processing, (8 December 1977); doi: 10.1117/12.955715
Show Author Affiliations
Harvey R. Seliner, The Perkin-Elmer Corporation (United States)

Published in SPIE Proceedings Vol. 0119:
Applications of Digital Image Processing
Andrew G. Tescher, Editor(s)

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