Share Email Print

Proceedings Paper

Effect Of Plastic Deformation Of Silicon Wafers On Overlay
Author(s): R. E. Gegenwarth; F. P. Laming
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Direct measurement of lateral distortion in (100) silicon wafers reveals random shifts as large as 0.5 μm resulting from high-temperature processes commonly used during the manufacture of integrated circuits. Such shifts are commensurate in size with the dimensional tolerances required for high-performance integrated circuits, and therefore pose a serious problem in the manufacture of devices requiring submicrometer lines or overlay accuracy of less than 1 μm. The effect has been studied after processing in various conditions; the lateral or in-plane distortions appear to increase as wafers undergo multiple-processing steps.

Paper Details

Date Published: 8 August 1977
PDF: 8 pages
Proc. SPIE 0100, Developments in Semiconductor Microlithography II, (8 August 1977); doi: 10.1117/12.955355
Show Author Affiliations
R. E. Gegenwarth, IBM System Products Division (United States)
F. P. Laming, I BMSystem Products Division (United States)

Published in SPIE Proceedings Vol. 0100:
Developments in Semiconductor Microlithography II
James W. Giffin, Editor(s)

© SPIE. Terms of Use
Back to Top