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Proceedings Paper

Parallel tools in HEVC for high-throughput processing
Author(s): Minhua Zhou; Vivienne Sze; Madhukar Budagavi
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Paper Abstract

HEVC (High Efficiency Video Coding) is the next-generation video coding standard being jointly developed by the ITU-T VCEG and ISO/IEC MPEG JCT-VC team. In addition to the high coding efficiency, which is expected to provide 50% more bit-rate reduction when compared to H.264/AVC, HEVC has built-in parallel processing tools to address bitrate, pixel-rate and motion estimation (ME) throughput requirements. This paper describes how CABAC, which is also used in H.264/AVC, has been redesigned for improved throughput, and how parallel merge/skip and tiles, which are new tools introduced for HEVC, enable high-throughput processing. CABAC has data dependencies which make it difficult to parallelize and thus limit its throughput. The prediction error/residual, represented as quantized transform coefficients, accounts for the majority of the CABAC workload. Various improvements have been made to the context selection and scans in transform coefficient coding that enable CABAC in HEVC to potentially achieve higher throughput and increased coding gains relative to H.264/AVC. The merge/skip mode is a coding efficiency enhancement tool in HEVC; the parallel merge/skip breaks dependency between the regular and merge/skip ME, which provides flexibility for high throughput and high efficiency HEVC encoder designs. For ultra high definition (UHD) video, such as 4kx2k and 8kx4k resolutions, low-latency and real-time processing may be beyond the capability of a single core codec. Tiles are an effective tool which enables pixel-rate balancing among the cores to achieve parallel processing with a throughput scalable implementation of multi-core UHD video codec. With the evenly divided tiles, a multi-core video codec can be realized by simply replicating single core codec and adding a tile boundary processing core on top of that. These tools illustrate that accounting for implementation cost when designing video coding algorithms can enable higher processing speed and reduce implementation cost, while still delivering high coding efficiency in the next generation video coding standard.

Paper Details

Date Published: 15 October 2012
PDF: 13 pages
Proc. SPIE 8499, Applications of Digital Image Processing XXXV, 849910 (15 October 2012); doi: 10.1117/12.953686
Show Author Affiliations
Minhua Zhou, Texas Instruments Inc. (United States)
Vivienne Sze, Texas Instruments Inc. (United States)
Madhukar Budagavi, Texas Instruments Inc. (United States)

Published in SPIE Proceedings Vol. 8499:
Applications of Digital Image Processing XXXV
Andrew G. Tescher, Editor(s)

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